PIC18F25K22-I/SP Microchip Technology Inc., PIC18F25K22-I/SP Datasheet - Page 387

• Manufacturer Part Number: PIC18F25K22-I/SP
• Description: 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F25K22-I/SP

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

DECFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
PC
CNT
If CNT
If CNT
Q1
No
Q1
Q1
No
No
PC =
PC =
=
=
=

register ‘f’
operation
operation
operation
Decrement f, skip if 0
DECFSZ f {,d {,a}}
0  f  255
d  [0,1]
a  [0,1]
(f) – 1  dest,
skip if result = 0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is ‘0’, the next instruction,
which is already fetched, is discarded
and a NOP is executed instead, making
it a two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note: 3 cycles if skip and followed
HERE
CONTINUE
Read
0010
Q2
No
Q2
No
No
Q2
Address (HERE)
CNT - 1
0;
Address (CONTINUE)
0;
Address (HERE + 2)
by a 2-word instruction.
11da
DECFSZ
GOTO
operation
operation
operation
Process
Data
Q3
No
Q3
No
No
Q3
ffff
for details.
CNT, 1, 1
LOOP
destination
operation
operation
operation
Write to
Q4
Q4
No
Q4
No
No
ffff
Preliminary
DCFSNZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
operation
operation
operation
Decode
TEMP
TEMP
If TEMP
If TEMP
Q1
Q1
No
Q1
No
No
PC
PC
register ‘f’
operation
operation
operation
Decrement f, skip if not 0
DCFSNZ
0  f  255
d  [0,1]
a  [0,1]
(f) – 1  dest,
skip if result  0
None
The contents of register ‘f’ are
decremented. If ‘d’ is ‘0’, the result is
placed in W. If ‘d’ is ‘1’, the result is
placed back in register ‘f’ (default).
If the result is not ‘0’, the next
instruction, which is already fetched, is
discarded and a NOP is executed
instead, making it a two-cycle
instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f 95 (5Fh). See
Section 25.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode”
1
1(2)
Note:
HERE
ZERO
NZERO
Read
0100
Q2
Q2
No
Q2
No
No
3 cycles if skip and followed
by a 2-word instruction.
=
=
=
=

=
DCFSNZ
:
:
f {,d {,a}}
11da
?
TEMP – 1,
0;
Address (ZERO)
0;
Address (NZERO)
operation
operation
operation
Process
Data
Q3
Q3
No
Q3
No
No
DS41412D-page 387
TEMP, 1, 0
ffff
for details.
destination
operation
operation
operation
Write to
Q4
Q4
Q4
No
No
No
ffff