PIC18F25K22-I/SP Microchip Technology Inc., PIC18F25K22-I/SP Datasheet - Page 377

• Manufacturer Part Number: PIC18F25K22-I/SP
• Description: 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F25K22-I/SP

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

BNC
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
 2010 Microchip Technology Inc.
Q Cycle Activity:
If Jump:
If No Jump:
Before Instruction
After Instruction
operation
Decode
Decode
PC
If CARRY
If CARRY
Q1
Q1
No
PC
PC
Read literal
Read literal
operation
Branch if Not Carry
BNC
-128  n  127
if CARRY bit is ‘0’
(PC) + 2 + 2n  PC
None
If the CARRY bit is ‘0’, then the program
will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0011
BNC
operation
Process
Process
Data
Data
Q3
No
Q3
Jump
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn
Preliminary
BNN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If Jump:
If No Jump:
PIC18(L)F2X/4XK22
Before Instruction
After Instruction
operation
Decode
Decode
PC
If NEGATIVE =
If NEGATIVE =
Q1
No
Q1
PC
PC
Read literal
Read literal
operation
Branch if Not Negative
BNN
-128  n  127
if NEGATIVE bit is ‘0’
(PC) + 2 + 2n  PC
None
If the NEGATIVE bit is ‘0’, then the
program will branch.
The 2’s complement number ‘2n’ is
added to the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is then a
two-cycle instruction.
1
1(2)
HERE
1110
Q2
No
Q2
‘n’
‘n’
=
=
=
n
address (HERE)
0;
address (Jump)
1;
address (HERE + 2)
0111
BNN
operation
Process
Process
Data
Data
Q3
No
Q3
DS41412D-page 377
Jump
nnnn
Write to PC
operation
operation
Q4
Q4
No
No
nnnn