PIC18F25K22-I/SP Microchip Technology Inc., PIC18F25K22-I/SP Datasheet - Page 313

• Manufacturer Part Number: PIC18F25K22-I/SP
• Description: 32KB, Flash, 1536bytes-RAM, 8-bit Family, nanoWatt XLP, 28 SPDIP .300in TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC18F25K22-I/SP

• A/d Inputs: 17-Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 24
• Interface: I2C/SPI/UART/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SPDIP
• Programmable Memory: 32K Bytes
• Ram Size: 1.5K Bytes
• Speed: 64 MHz
• Temperature Range: –40 to 125 °C
• Timers: 3-8-bit, 4-16-bit
• Voltage, Range: 1.8-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

18.8
There are four additional comparator features:
• Simultaneous read of comparator outputs
• Internal reference selection
• Hysteresis selection
• Output Synchronization
18.8.1
The MC1OUT and MC2OUT bits of the CM2CON1
register are mirror copies of both comparator outputs.
The ability to read both outputs simultaneously from a
single register eliminates the timing skew of reading
separate registers.
18.8.2
There are two internal voltage references available to
the non-inverting input of each comparator. One of
these is the Fixed Voltage Reference (FVR) and the
other is the variable Digital-to-Analog Converter (DAC).
The CxRSEL bit of the CM2CON1 register determines
which of these references is routed to the Comparator
Voltage reference output (C
the comparator is accomplished by the CxR bit of the
CMxCON0 register. See
Reference (FVR)”
 2010 Microchip Technology Inc.
Note 1: Obtaining the status of C1OUT or
Additional Comparator Features
SIMULTANEOUS COMPARATOR
OUTPUT READ
INTERNAL REFERENCE
SELECTION
C2OUT by reading CM2CON1 does not
affect the comparator interrupt mismatch
registers.
and
Figure 18-2
Section 21.0 “Fixed Voltage
X
V
REF
). Further routing to
for more detail.
Preliminary
18.8.3
Each Comparator has a selectable hysteresis feature.
The hysteresis can be enabled by setting the CxHYS
bit of the CM2CON1 register. See
trical Characteristics”
18.8.4
The Comparator Cx output can be synchronized with
Timer1 by setting the CxSYNC bit of the CM2CON1
register. When enabled, the Cx output is latched on
the falling edge of the Timer1 source clock. To prevent
a race condition when gating Timer1 clock with the
comparator output, Timer1 increments on the rising
edge of its clock source, and the falling edge latches
the comparator output. See the Comparator Block
Diagram
(Figure
Note 1: The comparator synchronized output
PIC18(L)F2X/4XK22
12-1) for more information.
2: The Timer1 prescale should be set to 1:1
(Figure
COMPARATOR HYSTERESIS
SYNCHRONIZING COMPARATOR
OUTPUT TO TIMER1
should not be used to gate the external
Timer1
synchronizer is enabled.
when synchronizing the comparator
output as unexpected results may occur
with other prescale values.
18-2) and the Timer1 Block Diagram
clock
for more details.
when
Section 27.0 “Elec-
DS41412D-page 313
the
Timer1