PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 25

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

3.0
As Harvard architecture devices, PIC24F micro-
controllers feature separate program and data memory
spaces and busses. This architecture also allows the
direct access of program memory from the data space
during code execution.
3.1
The
PIC24FJ64GA004 family devices is 4M instructions.
The space is addressable by a 24-bit value derived
FIGURE 3-1:
© 2007 Microchip Technology Inc.
Note:
Device Config Registers
program
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
MEMORY ORGANIZATION
Program Address Space
(5.5K instructions)
PIC24FJ16GA
Program Memory
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Memory areas are not shown to scale.
Read ‘0’
address
PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
memory
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
PIC24FJ32GA
Program Memory
(11K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
space
PIC24FJ64GA004 FAMILY
Preliminary
of
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
from either the 23-bit Program Counter (PC) during pro-
gram execution, or from table operation or data space
remapping, as described in Section 3.3 “Interfacing
Program and Data Memory Spaces”.
User access to the program memory space is restricted
to the lower half of the address range (000000h to
7FFFFFh). The exception is the use of TBLRD/TBLWT
operations which use TBLPAG<7> to permit access to
the Configuration bits and device ID sections of the
configuration memory space.
Memory maps for the PIC24FJ64GA004 family of
devices are shown in Figure 3-1.
Program Memory
(16K instructions)
PIC24FJ48GA
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
Device Config Registers
Alternate Vector Table
Interrupt Vector Table
Flash Config Words
PIC24FJ64GA
Program Memory
(22K instructions)
GOTO Instruction
Unimplemented
Reset Address
User Flash
DEVID (2)
Reserved
Reserved
Reserved
Read ‘0’
DS39881B-page 23
000000h
000002h
000004h
0000FEh
000100h
000104h
0001FEh
000200h
002BFEh
002C00h
0057FEh
005800h
0083FEh
008400h
00ABFEh
00AC00h
7FFFFFh
800000h
F7FFFEh
F80000h
F8000Eh
F80010h
FEFFFEh
FF0000h
FFFFFFh