PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 156

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PIC24FJ64GA002-I/SO

Manufacturer Part Number
PIC24FJ64GA002-I/SO
Description
MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC24FJ64GA002-I/SO

A/d Inputs
10 Channel, 10-Bit
Comparators
2
Cpu Speed
16 MIPS
Eeprom Memory
0 Bytes
Input Output
21
Interface
I2C/SPI/UART
Memory Capacity
64 Kbytes
Memory Type
Flash
Number Of Bits
16
Number Of Inputs
21
Number Of Pins
28
Package Type
28-pin SOIC
Programmable Memory
64K Bytes
Ram Size
8K Bytes
Speed
32 MHz
Timers
5-16-bit
Voltage, Range
2-3.6 V
Voltage, Rating
2-3.6 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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0
PIC24FJ64GA004 FAMILY
16.1
The UART module includes a dedicated 16-bit Baud
Rate Generator. The UxBRG register controls the
period of a free-running, 16-bit timer. Equation 16-1
shows the formula for computation of the baud rate
with BRGH = 0.
EQUATION 16-1:
Example 16-1 shows the calculation of the baud rate
error for the following conditions:
• F
• Desired Baud Rate = 9600
EXAMPLE 16-1:
DS39881B-page 154
Note 1:
Desired Baud Rate
Solving for UxBRG value:
Calculated Baud Rate= 4000000/(16 (25 + 1))
Error
Note 1:
CY
= 4 MHz
2:
UART Baud Rate Generator (BRG)
UxBRG
UxBRG
UxBRG
Baud Rate =
UxBRG =
F
frequency (F
Based on T
PLL are disabled.
Based on T
CY
denotes the instruction cycle clock
UART BAUD RATE WITH
BRGH = 0
BAUD RATE ERROR CALCULATION (BRGH = 0)
= F
= ((F
= ((4000000/9600)/16) – 1
= 25
= 9615
= (Calculated Baud Rate – Desired Baud Rate)
= (9615 – 9600)/9600
= 0.16%
16 • (UxBRG + 1)
CY
16 • Baud Rate
CY
OSC
Desired Baud Rate
= T
CY
CY
= T
/2).
/(16 (UxBRG + 1))
F
CY
F
CY
/Desired Baud Rate)/16) – 1
CY
CY
/2; Doze mode and
/2; Doze mode and PLL are disabled.
(1,2)
– 1
Preliminary
The maximum baud rate (BRGH = 0) possible is
F
possible is F
Equation 16-2 shows the formula for computation of
the baud rate with BRGH = 1.
EQUATION 16-2:
The maximum baud rate (BRGH = 1) possible is F
(for UxBRG = 0) and the minimum baud rate possible
is F
Writing a new value to the UxBRG register causes the
BRG timer to be reset (cleared). This ensures the BRG
does not wait for a timer overflow before generating the
new baud rate.
CY
Note 1:
CY
/16 (for UxBRG = 0) and the minimum baud rate
/(4 * 65536).
2:
Baud Rate =
UxBRG =
CY
F
frequency.
Based on T
PLL are disabled.
CY
/(16 * 65536).
(1)
denotes the instruction cycle clock
UART BAUD RATE WITH
BRGH = 1
© 2007 Microchip Technology Inc.
CY
4 • (UxBRG + 1)
4 • Baud Rate
= T
F
CY
F
CY
CY
/2; Doze mode and
(1,2)
– 1
CY
/4

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