PIC24FJ64GA002-I/SO Microchip Technology Inc., PIC24FJ64GA002-I/SO Datasheet - Page 160

• Manufacturer Part Number: PIC24FJ64GA002-I/SO
• Description: MCU, 16-Bit, 28-Pin, 64KB Flash, 8KB RAM, 21 I/O, Nanowatt
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ64GA002-I/SO

• A/d Inputs: 10 Channel, 10-Bit
• Comparators: 2
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 21
• Interface: I2C/SPI/UART
• Memory Capacity: 64 Kbytes
• Memory Type: Flash
• Number Of Bits: 16
• Number Of Inputs: 21
• Number Of Pins: 28
• Package Type: 28-pin SOIC
• Programmable Memory: 64K Bytes
• Ram Size: 8K Bytes
• Speed: 32 MHz
• Timers: 5-16-bit
• Voltage, Range: 2-3.6 V
• Voltage, Rating: 2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ64GA004 FAMILY
REGISTER 16-2:
DS39881B-page 158
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15,13
bit 14
bit 12
bit 11
bit 10
bit 9
bit 8
Note 1:
URXISEL1
UTXISEL1
R/W-0
R/W-0
2:
Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled
(IREN = 1).
If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin.
See Section 9.4 “Peripheral Pin Select” for more information
UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits
11 = Reserved; do not use
10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result,
01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit
00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at
UTXINV: IrDA
IREN = 0:
1 = UxTX Idle ‘0’
0 = UxTX Idle ‘1’
IREN = 1:
1 = UxTX Idle ‘1’
0 = UxTX Idle ‘0’
Unimplemented: Read as ‘0’
UTXBRK: Transmit Break bit
1 = Send Sync Break on next transmission – Start bit, followed by twelve ‘0’ bits, followed by Stop bit;
0 = Sync Break transmission disabled or completed
UTXEN: Transmit Enable bit
1 = Transmit enabled, UxTX pin controlled by UARTx
0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by
UTXBF: Transmit Buffer Full Status bit (Read-Only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written
TRMT: Transmit Shift Register Empty bit (Read-Only)
1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has
0 = Transmit Shift Register is not empty, a transmission is in progress or queued
URXISEL0
UTXINV
R/W-0
R/W-0
cleared by hardware upon completion
PORT.
completed)
UxSTA: UARTx STATUS AND CONTROL REGISTER
the transmit buffer becomes empty
operations are completed
least one character open in the transmit buffer)
(1)
®
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
UTXISEL0
Encoder Transmit Polarity Inversion bit
ADDEN
R/W-0
R/W-0
(2)
RIDLE
U-0
R-1
Preliminary
—
U = Unimplemented bit, read as ‘0’
HC = Hardware Clearable bit
‘0’ = Bit is cleared
R/W-0 HC
UTXBRK
PERR
R-0
(1)
UTXEN
R/W-0
FERR
R-0
(2)
© 2007 Microchip Technology Inc.
x = Bit is unknown
UTXBF
OERR
R/C-0
R-0
URXDA
TRMT
R-1
R-0
bit 8
bit 0