PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 89

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

TABLE 6-3:
 2010 Microchip Technology Inc.
POR
BOR
MCLR
WDT
Software
Illegal Opcode
Uninitialized W
Trap Conflict
Note 1:
Reset Type
(7)
2:
3:
4:
5:
6:
7:
T
T
WUTSEL<1:0> bits setting).
T
T
oscillator clock to the system.
T
T
If Two-speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC
so the system clock delay is just T
primary oscillator after its respective clock delay.
STARTUP
OST
RST
POR
LOCK
FRC
= Internal State Reset time (32 s nominal).
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the
and T
= Power-on Reset delay (10 s nominal).
RESET DELAY TIMES FOR VARIOUS DEVICE RESETS
= PLL lock time.
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
EC
ECPLL
XT, HS, SOSC
XTPLL, HSPLL
FRC, FRCDIV
FRCPLL
LPRC
Any Clock
Any Clock
Any clock
Any Clock
Any Clock
Any Clock
= T
LPRC
VREG
Clock Source
= RC Oscillator start-up times.
(10 s nominal when VREGS = 1 and when VREGS = 0; depends upon
FRC
PIC24FJ256GB210 FAMILY
, and in such cases, FRC start-up time is valid. It switches to the
T
T
T
T
T
T
T
POR
POR
POR
POR
POR
POR
POR
T
T
T
T
T
T
T
SYSRST Delay
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
+ T
+ T
+ T
+ T
+ T
+ T
+ T
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
STARTUP
T
T
T
T
T
T
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
+ T
+ T
+ T
+ T
+ T
+ T
+ T
RST
RST
RST
RST
RST
RST
RST
System Clock
T
T
T
T
OST
OST
FRC
FRC
T
T
Delay
T
T
T
T
T
T
LOCK
LPRC
LOCK
LPRC
OST
+ T
OST
+ T
FRC
+ T
FRC
+ T
—
—
—
—
—
—
—
—
LOCK
LOCK
LOCK
LOCK
DS39975A-page 89
1, 2, 3
1, 2, 3, 5
1, 2, 3, 4
1, 2, 3, 4, 5
1, 2, 3, 6, 7
1, 2, 3, 5, 6
1, 2, 3, 6
2, 3
2, 3, 5
2, 3, 4
2, 3, 4, 5
2, 3, 6, 7
2, 3, 5, 6
2, 3, 6
3
3
3
3
3
3
Notes