PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 221

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 16-1:
 2010 Microchip Technology Inc.
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
ACKDT: Acknowledge Data bit (when operating as I
Value that will be transmitted when the software initiates an Acknowledge sequence.
1 = Sends NACK during Acknowledge
0 = Sends ACK during Acknowledge
ACKEN: Acknowledge Sequence Enable bit (when operating as I
receive)
1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits the ACKDT data bit.
0 = Acknowledge sequence is not in progress
RCEN: Receive Enable bit (when operating as I
1 = Enables Receive mode for I
0 = Receive sequence is not in progress
PEN: Stop Condition Enable bit (when operating as I
1 = Initiates Stop condition on the SDAx and SCLx pins. Hardware is clear at the end of the master
0 = Stop condition is not in progress
RSEN: Repeated Start Condition Enabled bit (when operating as I
1 = Initiates Repeated Start condition on the SDAx and SCLx pins. Hardware is clear at the end of the
0 = Repeated Start condition is not in progress
SEN: Start Condition Enabled bit (when operating as I
1 = Initiates Start condition on SDAx and SCLx pins. Hardware is clear at end of the master Start
0 = Start condition is not in progress
Hardware is clear at the end of the master Acknowledge sequence.
data byte.
Stop sequence.
master Repeated Start sequence
sequence.
I2CxCON: I2Cx CONTROL REGISTER (CONTINUED)
PIC24FJ256GB210 FAMILY
2
C. Hardware is clear at the end of the eighth bit of the master receive
2
C master)
2
2
C master. Applicable during master receive.)
C master)
2
C master)
2
2
C master; applicable during master
C master)
DS39975A-page 221