PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 81

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

REGISTER 5-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
HC = Hardware Clearable bit
bit 15
bit 14
bit 13
bit 12-7
bit 6
bit 5-4
bit 3-0
Note 1:
R/S-0, HC
WR
U-0
—
2:
3:
(1)
These bits can only be reset on POR.
All other combinations of NVMOP<3:0> are unimplemented.
Available in ICSP™ mode only; refer to the device programming specification.
WR: Write Control bit
1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is
0 = Program or erase operation is complete and inactive
WREN: Write Enable bit
1 = Enables Flash program/erase operations
0 = Inhibits Flash program/erase operations
WRERR: Write Sequence Error Flag bit
1 = An improper program or erase sequence attempt, or termination has occurred (bit is set
0 = The program or erase operation completed normally
Unimplemented: Read as ‘0’
ERASE: Erase/Program Enable bit
1 = Performs the erase operation specified by NVMOP<3:0> on the next WR command
0 = Performs the program operation specified by NVMOP<3:0> on the next WR command
Unimplemented: Read as ‘0’
NVMOP<3:0>: NVM Operation Select bits
1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)
0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1)
0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0)
0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1)
R/W-0
R/W-0
ERASE
WREN
cleared by hardware once the operation is complete
automatically on any set attempt of the WR bit)
NVMCON: FLASH MEMORY CONTROL REGISTER
(1)
(1)
S = Settable bit
W = Writable bit
‘1’ = Bit is set
R-0, HSC
WRERR
U-0
—
(1)
(1)
(1)
PIC24FJ256GB210 FAMILY
U-0
U-0
—
—
(1)
(1)
(1,2)
HSC = Hardware Settable/Clearable bit
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
NVMOP3
R/W-0
U-0
—
(1)
(2)
NVMOP2
R/W-0
U-0
—
(1)
(2)
x = Bit is unknown
NVMOP1
R/W-0
U-0
—
(3)
(1)
(2)
DS39975A-page 81
NVMOP0
R/W-0
U-0
—
(1)
bit 8
bit 0
(2)