PIC24FJ256GB206-I/MR Microchip Technology Inc., PIC24FJ256GB206-I/MR Datasheet - Page 262

• Manufacturer Part Number: PIC24FJ256GB206-I/MR
• Description: 16-bit, 256KB Flash, 96K RAM, USB, 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB206-I/MR

• A/d Inputs: 16 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 52
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 64-pin QFN
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC24FJ256GB210 FAMILY
REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY)
DS39975A-page 262
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/K-0, HS
Note:
STALLIF
U-0
—
Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the
entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause
all set bits at the moment of the write to become cleared.
Unimplemented: Read as ‘0’
STALLIF: STALL Handshake Interrupt bit
1 = A STALL handshake was sent by the peripheral device during the handshake phase of the
0 = A STALL handshake has not been sent
ATTACHIF: Peripheral Attach Interrupt bit
1 = A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and
0 = No peripheral attacement has been detected
RESUMEIF: Resume Interrupt bit
1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for
0 = No K-state is observed
IDLEIF: Idle Detect Interrupt bit
1 = Idle condition is detected (constant Idle state of 3 ms or more)
0 = No Idle condition is detected
TRNIF: Token Processing Complete Interrupt bit
1 = Processing of the current token is complete; read the U1STAT register for endpoint information
0 = Processing of the current token not complete; clear the U1STAT register or load the next token
SOFIF: Start-of-Frame Token Interrupt bit
1 = A Start-of-Frame token received by the peripheral or the Start-of-Frame threshold reached by the host
0 = No Start-of-Frame token received or threshold reached
UERRIF: USB Error Condition Interrupt bit
1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set
0 = No unmasked error condition has occurred
DETACHIF: Detach Interrupt bit
1 = A peripheral detachment has been detected by the module; Reset state must be cleared before
0 = No peripheral detachment is detected. Individual bits can only be cleared by writing a ‘1’ to the bit
ATTACHIF
R/K-0, HS
transaction in Device mode
there has been no bus activity for 2.5 s
full speed)
from U1STAT
this bit
this bit can be reasserted
position as part of a word write operation on the entire register. Using Boolean instructions or bit-
wise operations to write to a single bit position will cause all set bits at the moment of the write to
become cleared.
U-0
—
K = Write ‘1’ to clear bit
U = Unimplemented bit, read as ‘0’
‘1’ = Bit is set
RESUMEIF
R/K-0, HS
U-0
—
R/K-0, HS
IDLEIF
U-0
—
HS = Hardware Settable bit
‘0’ = Bit is cleared
R/K-0, HS
TRNIF
U-0
—
R/K-0, HS
SOFIF
U-0
—
 2010 Microchip Technology Inc.
x = Bit is unknown
UERRIF
U-0
R-0
—
DETACHIF
R/K-0, HS
U-0
—
bit 8
bit 0