PIC24FJ256GB210-I/PT Microchip Technology Inc., PIC24FJ256GB210-I/PT Datasheet - Page 379

• Manufacturer Part Number: PIC24FJ256GB210-I/PT
• Description: 100 TQFP 12x12x1mm TRAY, 16-bit, 256KB Flash, 96K RAM, USB
• Manufacturer: Microchip Technology Inc.

Specifications of PIC24FJ256GB210-I/PT

• A/d Inputs: 24 Channel, 10-bit
• Comparators: 3
• Cpu Speed: 16 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 84
• Interface: I2C/SPI/UART/USART/USB
• Memory Type: Flash
• Number Of Bits: 16
• Package Type: 100-pin TQFP
• Programmable Memory: 256K Bytes
• Ram Size: 98K Bytes
• Speed: 32 MHz
• Temperature Range: –40 to 85 °C
• Timers: 5-16-bit
• Voltage, Range: 2.2-3.6 V
• Lead Free Status / Rohs Status: RoHS Compliant part

M
Memory Organization.......................................................... 43
Microchip Internet Web Site .............................................. 382
MPLAB ASM30 Assembler, Linker, Librarian ................... 336
MPLAB Integrated Development Environment
MPLAB PM3 Device Programmer .................................... 338
MPLAB REAL ICE In-Circuit Emulator System................. 337
MPLINK Object Linker/MPLIB Object Librarian ................ 336
N
Near Data Space ................................................................ 47
O
Oscillator Configuration
Output Compare
Output Compare with Dedicated Timers ........................... 195
P
Packaging ......................................................................... 363
Peripheral Enable Bits ...................................................... 150
Peripheral Module Disable Bits ......................................... 150
Peripheral Pin Select (PPS) .............................................. 158
Pin Descriptions
Pin Diagrams
Pinout Descriptions ............................................................. 20
POR
Power-Saving Features .................................................... 149
Power-up Requirements ................................................... 330
Product Identification System ........................................... 384
Program Memory
 2010 Microchip Technology Inc.
Software.................................................................... 335
96 MHz PLL .............................................................. 144
Clock Selection ......................................................... 138
Clock Switching......................................................... 143
CPU Clocking Scheme ............................................. 138
Initial Configuration on POR ..................................... 138
USB Operations ........................................................ 146
32-Bit Mode (Cascaded) ........................................... 195
Synchronous and Trigger Modes.............................. 195
Details ....................................................................... 364
Marking ..................................................................... 363
Available Peripherals and Pins ................................. 158
Configuration Control ................................................ 161
Considerations for Use ............................................. 162
Input Mapping ........................................................... 158
Mapping Exceptions.................................................. 161
Output Mapping ........................................................ 160
Peripheral Priority ..................................................... 158
Registers................................................................... 163
100-Pin Devices............................................................ 8
121-Pin (BGA) Devices............................................... 11
64-Pin Devices.............................................................. 6
100-Pin TQFP ............................................................... 7
121-Pin BGA ............................................................... 10
64-Pin TQFP/QFN ........................................................ 5
and On-Chip Voltage Regulator................................ 330
Clock Frequency and Clock Switching...................... 149
Instruction-Based Modes .......................................... 149
Access Using Table Instructions................................. 74
Address Construction.................................................. 72
Address Space............................................................ 43
Flash Configuration Words ......................................... 44
Memory Maps ............................................................. 43
Organization................................................................ 44
Reading From Program Memory Using EDS.............. 75
Sequence.......................................................... 143
PIC24FJ256GB210 FAMILY
Program Verification ......................................................... 332
Pulse-Width Modulation (PWM) Mode.............................. 197
Pulse-Width Modulation. See PWM.
PWM
R
Reader Response............................................................. 383
Reference Clock Output ................................................... 147
Register Maps
Registers
Duty Cycle and Period.............................................. 198
A/D Converter............................................................. 59
ANCFG ....................................................................... 62
ANSEL........................................................................ 62
Comparators............................................................... 64
CPU Core ................................................................... 48
CRC............................................................................ 64
CTMU ......................................................................... 60
I
ICN ............................................................................. 49
Input Capture.............................................................. 52
Interrupt Controller...................................................... 50
NVM............................................................................ 67
Output Compare ......................................................... 53
Pad Configuration....................................................... 58
Peripheral Pin Select .................................................. 65
PMD............................................................................ 67
PORTA ....................................................................... 56
PORTB ....................................................................... 56
PORTC ....................................................................... 57
PORTD ....................................................................... 57
PORTE ....................................................................... 57
PORTF ....................................................................... 58
PORTG....................................................................... 58
RTCC.......................................................................... 63
SPI.............................................................................. 56
System........................................................................ 67
Timers......................................................................... 51
UART.......................................................................... 55
USB OTG ................................................................... 61
AD1CHS (A/D Input Select)...................................... 306
AD1CON1 (A/D Control 1)........................................ 303
AD1CON2 (A/D Control 2)........................................ 304
AD1CON3 (A/D Control 3)........................................ 305
AD1CSSH (A/D Input Scan Select, High)................. 308
AD1CSSL (A/D Input Scan Select, Low) .................. 307
ALCFGRPT (Alarm Configuration) ........................... 285
ALMINSEC (Alarm Minutes and Seconds Value)..... 289
ALMTHDY (Alarm Month and Day Value) ................ 288
ALWDHR (Alarm Weekday and Hours Value) ......... 289
ANCFG (A/D Band Gap Reference
ANSA (PORTA Analog Function Selection) ............. 153
ANSB (PORTB Analog Function Selection) ............. 154
ANSC (PORTC Analog Function Selection) ............. 154
ANSD (PORTD Analog Function Selection) ............. 155
ANSE (PORTE Analog Function Selection) ............. 155
ANSF (PORTF Analog Function Selection).............. 156
ANSG (PORTG Analog Function Selection) ............ 156
BDnSTAT Prototype (Buffer Descriptor n Status, CPU
BDnSTAT Prototype (Buffer Descriptor n
CLKDIV (Clock Divider) ............................................ 141
CMSTAT (Comparator Status) ................................. 315
2
C™........................................................................... 54
Configuration) ................................................... 307
Mode) ............................................................... 242
Status, USB Mode)........................................... 241
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