IDT82V2044EPFG8 IDT, Integrated Device Technology Inc, IDT82V2044EPFG8 Datasheet - Page 19
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IDT82V2044EPFG8
Manufacturer Part Number
IDT82V2044EPFG8
Description
IC LINE INTERFC UNIT 4CH 128TQFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Line Interface Units (LIUs)r
Datasheet
1.IDT82V2044EPFG8.pdf
(73 pages)
Specifications of IDT82V2044EPFG8
Protocol
E1
Voltage - Supply
3.13 V ~ 3.47 V
Mounting Type
Surface Mount
Package / Case
128-TQFP, 128-VQFP
Screening Level
Industrial
Mounting
Surface Mount
Package Type
TQFP
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Drivers/receivers
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant
Other names
800-1863-2
82V2044EPFG8
82V2044EPFG8
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDT82V2044EPFG8
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
3.3
Gain, Amplitude/Wave Shape Detector, Digital Tuning Controller, Adaptive
Equalizer, Data Slicer, CDR (Clock and Data Recovery), Optional Jitter
Attenuator, Decoder and LOS/AIS Detector. Refer to Figure-7.
3.3.1
matching circuit or the external impedance matching circuit. If R_TERM[2]
Table-11 Impedance Matching for Receiver
RTIP
RRING
The receive path consists of Receive Internal Termination, Monitor
The impedance matching can be realized by the internal impedance
Cable Configuration
RECEIVE PATH
RECEIVE INTERNAL TERMINATION
E1/120 Ω
E1/75 Ω
T1
J1
termination
Receive
Internal
Note: 1. Common decoupling capacitor
R
Monitor Gain
3. D1 - D8, Motorola - MBR0540T1;
2. Cp 0-560 (pF)
X
T
Line
X
Line
A
B
R_TERM[2:0]
•
•
Figure-7 Receive Path Function Block Diagram
1:1
2:1
000
001
010
011
Internal Termination
•
•
Figure-8 Transmit/Receive Line Circuit
Cp
Equalizer
Adaptive
2
R
R
•
•
R
R
VDDRn
T
T
D6
D5
International Rectifier - 11DQ04 or 10BQ060
•
·
VDDTn
VDDTn
VDDRn
D8
D7
D2
D1
D4
D3
Data Slicer
120 Ω
3
R
•
•
•
·
·
·
19
R
One of the Four Identical Channels
RTIPn
RRINGn
TTIPn
TRINGn
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 1AH...) can be set to choose 75 Ω, 100
Ω, 110 Ω or 120 Ω internal impedance of RTIPn/RRINGn. If R_TERM[2]
is set to ‘1’, the internal impedance matching circuit will be disabled. In this
case, the external impedance matching circuit will be used to realize the
impedance matching.
the cable for one channel.
ance matching for receiver.
Figure-8
Recovery
and Data
Clock
shows the appropriate external components to connect with
R_TERM[2:0]
GNDRn
VDDRn
GNDTn
1XX
VDDTn
Attenuator
Table-11
Jitter
External Termination
0.1µF
0.1µF
is the list of the recommended imped-
•
•
TEMPERATURE RANGES
LOS/AIS
Detector
Decoder
68µF
68µF
3.3 V
1
3.3 V
1
120 Ω
100 Ω
110 Ω
75 Ω
R
R
INDUSTRIAL
LOS
RCLK
RDN
RDP