PIC16F690-E/P Microchip Technology Inc., PIC16F690-E/P Datasheet - Page 84
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PIC16F690-E/P
Manufacturer Part Number
PIC16F690-E/P
Description
20 PIN, 7 KB FLASH, 256 RAM, 18 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F690-EP.pdf
(294 pages)
Specifications of PIC16F690-E/P
A/d Inputs
12-Channel, 10-Bit
Comparators
2
Cpu Speed
7 MIPS
Eeprom Memory
256 Bytes
Input Output
18
Interface
USART
Memory Type
Flash
Number Of Bits
8
Package Type
20-pin PDIP
Programmable Memory
7K Bytes
Ram Size
256 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
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PIC16F631/677/685/687/689/690
5.1.3
A single software programmable prescaler is available
for use with either Timer0 or the Watchdog Timer
(WDT), but not both simultaneously. The prescaler
assignment is controlled by the PSA bit of the OPTION
register. To assign the prescaler to Timer0, the PSA bit
must be cleared to a ‘0’.
There are 8 prescaler options for the Timer0 module
ranging from 1:2 to 1:256. The prescale values are
selectable via the PS<2:0> bits of the OPTION register.
In order to have a 1:1 prescaler value for the Timer0
module, the prescaler must be assigned to the WDT
module.
The prescaler is not readable or writable. When the
prescaler is assigned to the Timer0 module, all
instructions writing to the TMR0 register will clear the
prescaler.
When the prescaler is assigned to WDT, a CLRWDT
instruction will clear the prescaler along with the WDT.
5.1.3.1
As a result of having the prescaler assigned to either
Timer0 or the WDT, it is possible to generate an
unintended device Reset when switching prescaler
values. When changing the prescaler assignment from
Timer0 to the WDT module, the instruction sequence
shown in Example 5-1, must be executed.
EXAMPLE 5-1:
DS41262C-page 82
BANKSEL
CLRWDT
CLRF
BANKSEL
BSF
CLRWDT
MOVLW
ANDWF
IORLW
MOVWF
SOFTWARE PROGRAMMABLE
PRESCALER
TMR0
TMR0
OPTION_REG
OPTION_REG,PSA
b’11111000’
OPTION_REG,W
b’00000101’
OPTION_REG
Switching Prescaler Between
Timer0 and WDT Modules
CHANGING PRESCALER
(TIMER0
;
;Clear WDT
;Clear TMR0 and
; prescaler
;
;Select WDT
;
;
;Mask prescaler
; bits
;Set WDT prescaler
; to 1:32
WDT)
Preliminary
When changing the prescaler assignment from the
WDT to the Timer0 module, the following instruction
sequence must be executed (see Example 5-2).
EXAMPLE 5-2:
5.1.4
Timer0 will generate an interrupt when the TMR0
register overflows from FFh to 00h. The T0IF interrupt
flag bit of the INTCON register is set every time the
TMR0 register overflows, regardless of whether or not
the Timer0 interrupt is enabled. The T0IF bit must be
cleared in software. The Timer0 interrupt enable is the
T0IE bit of the INTCON register.
5.1.5
When Timer0 is in Counter mode, the synchronization
of the T0CKI input and the Timer0 register is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, the
high and low periods of the external clock source must
meet
Section 17.0 “Electrical Specifications”.
CLRWDT
BANKSEL OPTION_REG
MOVLW
ANDWF
IORLW
MOVWF
Note:
the
b’11110000’
OPTION_REG,W ; prescaler bits
b’00000011’
OPTION_REG
TIMER0 INTERRUPT
The Timer0 interrupt cannot wake the
processor from Sleep since the timer is
frozen during Sleep.
USING TIMER0 WITH AN
EXTERNAL CLOCK
timing
requirements
CHANGING PRESCALER
(WDT
© 2006 Microchip Technology Inc.
;Clear WDT and
;prescaler
;
;Mask TMR0 select and
;Set prescale to 1:16
;
TIMER0)
as
shown
in
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