PIC16F84A-04/P Microchip Technology Inc., PIC16F84A-04/P Datasheet - Page 28
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PIC16F84A-04/P
Manufacturer Part Number
PIC16F84A-04/P
Description
18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F84A-04P.pdf
(88 pages)
Specifications of PIC16F84A-04/P
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
13
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
68 Bytes
Speed
20 MHz
Timers
1-8-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84A-04/P
Manufacturer:
MICROCHIP
Quantity:
1 450
PIC16F84A
6.4
A Power-on Reset pulse is generated on-chip when
V
take advantage of the POR, just tie the MCLR pin
directly (or through a resistor) to V
eliminate external RC components usually needed to
create Power-on Reset. A minimum rise time for V
must be met for this to operate properly. See Electrical
Specifications for details.
When the device starts normal operation (exits the
RESET condition), device operating parameters (volt-
age, frequency, temperature, etc.) must be met to
ensure operation. If these conditions are not met, the
device must be held in RESET until the operating con-
ditions are met.
For additional information, refer to Application Note
AN607, " Power-up Trouble Shooting ."
The POR circuit does not produce an internal RESET
when V
6.5
The Power-up Timer (PWRT) provides a fixed 72 ms
nominal time-out (T
through 6-9). The Power-up Timer operates on an
internal RC oscillator. The chip is kept in RESET as
long as the PWRT is active. The PWRT delay allows
the V
tion shown in Figure 6-9).
A configuration bit, PWRTE, can enable/disable the
PWRT. See Register 6-1 for the operation of the
PWRTE bit for a particular device.
The power-up time delay T
chip due to V
See DC parameters for details.
DS35007B-page 26
DD
rise is detected (in the range of 1.2V - 1.7V). To
DD
DD
to rise to an acceptable level (possible excep-
Power-on Reset (POR)
Power-up Timer (PWRT)
declines.
DD
, temperature, and process variation.
PWRT
) from POR (Figures 6-6
PWRT
will vary from chip to
DD
. This will
DD
6.6
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle delay (from OSC1 input) after the
PWRT delay ends (Figure 6-6, Figure 6-7, Figure 6-8
and Figure 6-9). This ensures the crystal oscillator or
resonator has started and stabilized.
The OST time-out (T
HS modes and only on Power-on Reset or wake-up
from SLEEP.
When V
T
V
(Figure 6-9), an external Power-on Reset circuit may
be necessary (Figure 6-5).
FIGURE 6-5:
PWRT
DD
Note 1: External Power-on Reset circuit is required
has reached its final value. In this case
time-out and T
DD
V
Oscillator Start-up Timer (OST)
DD
2: R < 40 k
3: R1 = 100 to 1 k will limit any current flow-
rises very slowly, it is possible that the
D
only if V
diode D helps discharge the capacitor
quickly when V
that voltage drop across R does not exceed
0.2V (max leakage current spec on MCLR
pin is 5 A). A larger voltage drop will
degrade V
ing into MCLR from external capacitor C, in
the event of a MCLR pin breakdown due to
ESD or EOS.
V
DD
R
OST
C
DD
EXTERNAL POWER-ON
RESET CIRCUIT (FOR
SLOW V
OST
IH
) is invoked only for XT, LP and
power-up rate is too slow. The
is recommended to make sure
level on the MCLR pin.
2001 Microchip Technology Inc.
R1
DD
time-out will expire before
powers down.
DD
PIC16FXX
MCLR
POWER-UP)