PIC16F84A-04/P Microchip Technology Inc., PIC16F84A-04/P Datasheet - Page 19

• Manufacturer Part Number: PIC16F84A-04/P
• Description: 18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F84A-04/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 64 Bytes
• Input Output: 13
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin PDIP
• Programmable Memory: 1.75K Bytes
• Ram Size: 68 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

4.2
PORTB is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISB. Setting a
TRISB bit (= 1) will make the corresponding PORTB pin
an input (i.e., put the corresponding output driver in a
Hi-Impedance mode). Clearing a TRISB bit (= 0) will
make the corresponding PORTB pin an output (i.e., put
the contents of the output latch on the selected pin).
EXAMPLE 4-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is per-
formed by clearing bit RBPU (OPTION<7>). The weak
pull-up is automatically turned off when the port pin is
configured as an output. The pull-ups are disabled on a
Power-on Reset.
Four of PORTB’s pins, RB7:RB4, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB7:RB4 pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins (of RB7:RB4)
are compared with the old value latched on the last
read of PORTB. The “mismatch” outputs of RB7:RB4
are OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
BCF
CLRF
BSF
MOVLW
MOVWF
2001 Microchip Technology Inc.
Any read or write of PORTB. This will end the
mismatch condition.
Clear flag bit RBIF.
PORTB and TRISB Registers
STATUS, RP0 ;
PORTB
STATUS, RP0 ; Select Bank 1
0xCF
TRISB
INITIALIZING PORTB
; Initialize PORTB by
; clearing output
; data latches
; Value used to
; initialize data
; direction
; Set RB<3:0> as inputs
; RB<5:4> as outputs
; RB<7:6> as inputs
FIGURE 4-3:
FIGURE 4-4:
Set RBIF
Note 1:
Note 1:
RBPU
Data Bus
WR Port
WR TRIS
RBPU
Data Bus
WR Port
WR TRIS
RB0/INT
From other
RB7:RB4 pins
(1)
(1)
2:
2:
TRISB = ’1’ enables weak pull-up
(if RBPU = ’0’ in the OPTION_REG register).
I/O pins have diode protection to V
TRISB = ’1’ enables weak pull-up
I/O pins have diode protection to V
(if RBPU = ’0’ in the OPTION_REG register).
RD TRIS
RD Port
TRIS Latch
Data Latch
RD TRIS
RD Port
D
D
TRIS Latch
Data Latch
CK
CK
D
D
CK
CK
Schmitt Trigger
Buffer
BLOCK DIAGRAM OF
PINS RB7:RB4
BLOCK DIAGRAM OF
PINS RB3:RB0
Q
Q
Q
Q
PIC16F84A
Q
Q
Q
Latch
EN
EN
DS35007B-page 17
EN
TTL
Input
Buffer
D
D
D
DD
RD Port
DD
and V
and V
V
RD Port
P
V
DD
P
DD
Weak
Pull-up
I/O pin
Weak
Pull-up
I/O pin
TTL
Input
Buffer
SS
SS
.
.
(2)
(2)