PIC16F84A-04/P Microchip Technology Inc., PIC16F84A-04/P Datasheet - Page 26
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PIC16F84A-04/P
Manufacturer Part Number
PIC16F84A-04/P
Description
18 PIN, 1.75 KB FLASH, 68 RAM, 13 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F84A-04P.pdf
(88 pages)
Specifications of PIC16F84A-04/P
Cpu Speed
5 MIPS
Eeprom Memory
64 Bytes
Input Output
13
Memory Type
Flash
Number Of Bits
8
Package Type
18-pin PDIP
Programmable Memory
1.75K Bytes
Ram Size
68 Bytes
Speed
20 MHz
Timers
1-8-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
Electrostatic Device
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC16F84A-04/P
Manufacturer:
MICROCHIP
Quantity:
1 450
PIC16F84A
6.3
The PIC16F84A differentiates between various kinds
of RESET:
• Power-on Reset (POR)
• MCLR during normal operation
• MCLR during SLEEP
• WDT Reset (during normal operation)
• WDT Wake-up (during SLEEP)
Figure 6-4 shows a simplified block diagram of the
On-Chip RESET Circuit. The MCLR Reset path has a
noise filter to ignore small pulses. The electrical speci-
fications state the pulse width requirements for the
MCLR pin.
FIGURE 6-4:
TABLE 6-3:
DS35007B-page 24
Power-on Reset
MCLR during normal operation
MCLR during SLEEP
WDT Reset (during normal operation)
WDT Wake-up
Interrupt wake-up from SLEEP
Legend: u = unchanged, x = unknown
Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h).
MCLR
OSC1/
CLKIN
V
Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin.
DD
RESET
2: See Table 6-5.
RC Osc
On-Chip
OST/PWRT
V
Module
Detect
DD
WDT
RESET CONDITION FOR PROGRAM COUNTER AND THE STATUS REGISTER
(1)
Rise
SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT
OST
PWRT
Reset
WDT
Time-out
External Reset
10-bit Ripple Counter
10-bit Ripple Counter
Power-on Reset
SLEEP
Condition
Enable PWRT
Enable OST
Some registers are not affected in any RESET condition;
their status is unknown on a POR and unchanged in any
other RESET. Most other registers are reset to a “RESET
state” on POR, MCLR or WDT Reset during normal oper-
ation and on MCLR during SLEEP. They are not affected
by a WDT Reset during SLEEP, since this RESET is
viewed as the resumption of normal operation.
Table 6-3 gives a description of RESET conditions for
the program counter (PC) and the STATUS register.
Table 6-4 gives a full description of RESET states for all
registers.
The TO and PD bits are set or cleared differently in dif-
ferent RESET situations (Section 6.7). These bits are
used in software to determine the nature of the RESET.
Program Counter
PC + 1
PC + 1
See Table 6-5
000h
000h
000h
000h
(1)
2001 Microchip Technology Inc.
S
R
STATUS Register
Q
0001 1xxx
000u uuuu
0001 0uuu
0000 1uuu
uuu0 0uuu
uuu1 0uuu
Chip_Reset