CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 48

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
Receive FIFO Reset Sequence
The Receive FIFO reset sequence operates (for the most part)
the same as the Transmit FIFO reset sequence. The same
requirements exist for the assertion state of RXRST and
selection of the interface. A sample Receive FIFO reset
sequence is shown in
Receive FIFO reset, the Receive FIFO flags are forced to
Rx_FIFO_Reset
Rx_RstMatch
RXEMPTY
Rx_Match
RXRST
RXCLK
RXEN
CE
[49]
[49]
[49]
Figure
16. Upon recognition of a
Note 48
Figure 16. Receive FIFO Reset Sequence.
Note 48
Not Empty
indicate an EMPTY state to prohibit additional reads from the
FIFO. Unlike the Transmit FIFO, where the internal completion
of the reset operation is shown by first going FULL and later
going EMPTY when the internal reset is complete, there is no
secondary indication of the completion of the internal reset of
the Receive FIFO. The Receive FIFO is usable as soon as
new data is placed into it by the Receive Control State Machine
Empty
CY7C9689A
Page 48 of 51
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