CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 20

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
Table 4. CY7C9689A TAXI HOTLink BIST Sequence
Table 5. Receiver Discard Policies
D.00
C.JK
C.TR
D.89
D.15
D.A8
D.99
D.D1
C.SS
C.QQ D.FC
D.50
D.DD D.6E
C.TR
D.17
D.BD D.5E
C.HI
C.SS
C.TR
D.02
C.HH D.8A
D.14
C.TR
D.4D
C.HQ D.AF
C.SR C.SS
D.18
C.SS
C.QH D.DB D.67
C.TR
D.30
Policy #
2 (1X)
0 (00)
1 (01)
C.JK
C.IH
C.SR C.SS
D.42
D.0C
C.TT
D.46
D.64
C.QQ D.F0
C.SR C.QQ D.F6
D.0D
D.92
C.SS
C.QI
C.HH D.84
C.JK
C.SR C.SS
D.2A
C.JK
C.QQ D.F3
C.QI
C.JK
C.II
Keep all received characters
Process Commands, discard all but the last JK or
LM SYNC character
Process Commands, discard all C5.0 characters
Policy Description
C.IH
C.QI
C.HI
C.JK
C.QH D.D4
C.HI
C.II
C.TS
C.IH
C.HI
D.0A
C.HI
C.HQ D.AC C.TT
C.QQ D.F1
D.E9
C.HQ D.A5
C.IH
C.HH D.81
D.5B
C.SS
C.RS D.CE C.RR D.B7
D.E8
C.IH
C.HH D.85
D.9F
C.SR C.SS
D.EE
C.QQ D.F8
D.94
C.RS D.CD D.6A
D.96
C.IH
C.TS
C.QH D.D3
C.SR C.QQ D.FD
D.93
D.72
C.TT
C.QI
C.QQ D.F9
D.27
C.QQ D.F2
D.75
D.39
C.TS
C.SR C.QQ D.FE
C.RR D.B3
C.TT
C.TS
C.HQ D.AE
C.QI
C.TR
D.45
C.RR D.BA
D.4F
D.74
C.HI
C.TR
D.58
D.EF
D.40
D.19
D.3C
D.16
C.QH D.D0
D.48
D.2B
D.7B
D.06
C.HH D.8E
C.QQ D.FB
C.TS
C.TR
C.TR
D.E4
C.SR C.QQ D.F4
D.65
D.28
C.QH D.D5
C.II
D.98
C.QI
C.II
D.76
C.II
C.RR D.B8
C.JK
D.55
C.QH D.D2
C.QI
C.HI
C.QI
C.HQ D.A3
C.RR C.TR
D.38
D.7E
C.JK
C.HQ D.A9
C.II
D.13
C.IH
C.TT
D.EA
C.RS D.CA
D.37
C.HI
C.IH
C.HH D.86
D.5D
C.RS D.C7
C.TS
C.RR D.BB
D.77
D.2C
D.EB
D.91
D.E3
C.JK
C.HI
C.RS
C.RS
D.05
D.6C
C.QI
C.QH
C.RR
D.1D
D.9A
C.SR
C.TT
D.2E
C.HQ
C.TR
Receive FIFO and operation of the Receive Control State
Machine.
Receive Output Register
The Receive Output Register changes in response to the
rising edge of RXCLK. The Receive FIFO status flag outputs
of this register are placed in a High-Z state when the
CY7C9689A is not addressed (CE is sampled HIGH). The
D.3D
C.JK
C.RR D.BC C.TT
D.73
D.44
D.71
D.51
C.QI
C.TS
C.RS D.C6
D.9B
D.C4
D.52
D.C8
D.08
C.II
D.E5
D.DE C.RR D.BF
D.B1
C.RR D.B5
D.0E
C.HQ D.AD D.5A
C.SS
C.HQ D.A6
C.QH D.D6
C.HH D.83
D.69
D.A7
C.SR C.QQ D.F5
D.57
C.RS D.C5
C.HI
D.54
C.QQ D.FA
D.32
D.59
D.2D
D.1E
D.35
C.II
D.34
D.24
D.E0
C.TR
D.47
C.TS
C.TS
C.JK
C.RS D.C1
D.78
C.HH D.87
C.HH D.8F
D.1C
C.IH
C.JK
C.JK
C.TS
C.QI
C.RR D.B6
D.29
C.TR
D.9C
C.QH D.D8
C.RS D.CC C.TS
C.II
C.II
D.5C
C.HQ D.A2
C.RR D.BE
D.41
C.HH D.88
D.26
D.1A
D.68
C.QH D.D7
C.QI
C.IH
C.IH
C.TR
D.12
C.QI
C.TT
C.RS D.C2
D.5F
C.IH
C.II
D.49
C.HI
D.20
C.HH D.82
D.7C
C.HH D.8D
C.JK
D.E1
D.60
C.RR D.B9
D.4B
C.II
C.RS D.CF
D.E6
C.QI
C.QI
C.SR C.SS
D.70
C.HQ D.AA
C.HH D.8C
D.E2
C.QH D.DF
C.TS
C.II
D.2F
C.QI
C.RS D.CB D.63
D.22
D.9D
C.HQ D.AO C.TT
C.HQ D.AB
C.JK
C.TT
C.II
C.RS D.C0
C.RR D.B2
D.23
D.6D
D.ED D.7A
D.EC C.TS
C.II
C.RR D.B0
C.QH D.DA C.RR
C.QH D.D9
C.IH
C.RR D.B4
D.1B
D.E7
C.HH D.80
D.4E
D.56
C.IH
C.QH D.DC C.TS
C.HQ D.A4
C.RS D.C3
D.4A
CY7C9689A
D.11
D.3A
D.6B
C.SS
C.IH
C.HQ D.A1
C.TT
D.6F
C.SR C.SS
D.07
D.79
C.HI
C.HI
D.53
C.SR C.SS
C.HI
Page 20 of 51
D.04
C.TS
C.HH
D.33
C.HQ
C.HI
C.QH
C.SS
C.SR
C.QH
C.TT
D.3B
D.66
C.TT
D.09
D.36
D.31
C.TT
D.97
D.9E
C.TR
D.25
C.TT
D.61
D.95
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