CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 44

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
Continuous Selection
Continuous Selection is a specialized form of selection which
does not require sequenced assertion of CE and TXEN or
RXEN to select the device for data transfers. In this
Continuous Selection mode, the CE and associated TXEN or
RXEN enable signal must be asserted when the device is
powered up or during assertion of RESET. So long as these
signals remain asserted, the device remains selected and data
is accepted and presented on every clock cycle. Note: The
use of continuous selection makes it impossible to reset the
respective internal FIFOs, or to access the Serial Address
Register.
FIFO Reset Address Match
When CE and TXRST are both LOW, and this condition is
sampled by the rising edge of TXCLK, a Tx_RstMatch
condition is generated. This Tx_RstMatch condition continues
until CE or TXRST is sampled HIGH by the rising edge of
TXCLK. When a Tx_RstMatch (or Tx_Match) condition is
present, the TXEMPTY and TXFULL output drivers are
enabled (just as in a normal Tx_Match condition). When a
Tx_RstMatch (or Tx_Match) condition is not present, these
same drivers are disabled (High-Z). The Transmit FIFO reset
Address Match is shown in
TXRST remains LOW for more than one clock cycle, the
Tx_RstMatch does not because the CE signal is no longer
asserted (LOW).
When CE and RXRST are both LOW, and this condition is
sampled by the rising edge of RXCLK, an Rx_RstMatch
RXDATA/RXCMD
Rx_Selected
RXEMPTY
Rx_Match
RXRST
RXCLK
RXEN
CE
[46]
[46]
Figure
Figure 10. Receive Selection with Receive FIFO Enabled
11. Note that although
Note 47
Not Empty
Note 47
Not Empty
condition is generated. This Rx_RstMatch condition continues
until CE or RXRST is sampled HIGH, at the rising edge of
RXCLK. When an Rx_RstMatch (or Rx_Match) condition is
present, the RXEMPTY and RXFULL output drivers are
enabled. When an Rx_RstMatch (or Rx_Match) condition is
not present, these same drivers are disabled (High-Z). The
Receive FIFO reset Address Match is shown in
Note that while the FIFO flags remain asserted for more than
one clock cycle, this is due to an Rx_Match condition, not a
continuation of the Rx_RstMatch.
Tx_RstMatch
Figure 11. Transmit FIFO Reset Address Match
Tx_Match
D1
TXFULL
TXRST
TXCLK
CE
[46]
[46]
D2
D3
Valid
CY7C9689A
Page 44 of 51
Figure
12.
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