CY7C9689A-AXC Cypress Semiconductor Corp, CY7C9689A-AXC Datasheet - Page 42

• Manufacturer Part Number: CY7C9689A-AXC
• Description: IC TXRX HOTLINK 100LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: CY7Cr
• Type: Transceiverr

Specifications of CY7C9689A-AXC

• Package / Case: 100-LQFP
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Product: PHY
• Interface Type: Parallel
• Supply Voltage (max): 6.5 V
• Supply Voltage (min): 2 V
• Supply Current: 250 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Number Of Channels: 2
• Ic Interface Type: Parallel, Serial
• Supply Voltage Range: 4.5V To 5.5V
• Operating Temperature Range: 0°C To +70°C
• Digital Ic Case Style: TQFP
• No. Of Pins: 100
• Msl: MSL 3 - 168 Hours
• No. Of Receivers: 2
• Rohs Compliant: Yes
• Frequency Max: 50MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Document #: 38-02020 Rev. *E
The selection state of the Transmit Input Register is entered
when a Tx_Match condition is present, and TXEN transitions
from HIGH to LOW. Once selected, the transmit input register
remains selected until TXEN is sampled HIGH by the rising
edge of REFCLK. In the selected state, data present on the
TXDATA inputs is captured in the Transmit Input Register and
passed to the Serializer or Encoder (as selected by the
ENCBYP input). This transmit interface selection process is
shown in
When the 4B/5B Encoder is enabled and data is not written to
the Transmit Input Register, the data stream is automatically
padded with JK or LM SYNC characters. When the 4B/5B,
5B/6B Encoder is disabled and no data is written to the
Transmit Input Register, JK or LM SYNC characters are also
automatically padded with SYNC characters.
Notes
46. Signals shown as dotted lines indicate timing and levels when configured for external FIFOs (EXTFIFO is HIGH).
47. Signal names listed in italics are internal signals, shown for reference only.
TXDATA/TXCMD
TXDATA/TXCMD
(Shared Bus Timing)
(Cascade Timing)
Tx_Selected
Figure
Tx_Match
TXFULL
TXRST
TXCLK
TXEN
9.
CE
[46]
[46]
Figure 8. Transmit Selection with Transmit FIFO Enabled
Note 47
Note 47
Not Full
Receive Data Selection
Asynchronous With Shared Bus Timing and Control
(Receive FIFO Enabled)
When CE is sampled LOW and RXRST is sampled HIGH by
the rising edge of RXCLK input, an Rx_Match condition is
generated. This Rx_Match condition continues until CE is
sampled HIGH or RXRST is sampled LOW at the rising edge
of RXCLK input. When an Rx_Match (or Rx_RstMatch)
condition is present, the RXEMPTY and RXFULL output
drivers are enabled.
When an Rx_Match (or Rx_RstMatch) condition is not
present, these same drivers are disabled (High-Z).
Not Full
D1
D2
D1
D3
D2
D3
CY7C9689A
Page 42 of 51
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