E-STE100P STMicroelectronics, E-STE100P Datasheet - Page 9

• Manufacturer Part Number: E-STE100P
• Description: IC TRANSCEIVER 3.3V 64 TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of E-STE100P

• Number Of Drivers/receivers: 1/1
• Protocol: MII
• Voltage - Supply: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2143; STE100P

Table 5. Register Descriptions (continued)
R/W = Read/Write able. RO = Read Only.
PR1- XSR, XCVR Status Register. All the bits of this register are read only.
10~7
Bit #
6~0
11
10
15
14
13
12
11
9
8
7
COLEN
DPSEL
ISOEN
Name
PDEN
RSAN
TXHD
TXFD
10HD
10FD
T4
---
---
Power-down mode control.
1: Power-down mode is selected. Setting this bit puts the
STE100P into power-down mode. During the power-down
mode, TXP/TXN and all LED outputs are 3-stated, and the MII
interface is isolated.
0 – Normal operation.
1 – Isolate PHY from MII.
Setting this control bit isolates the STE100P from the MII, with
the exception of the serial management inter-face. When this
bit is asserted, the STE100Pdoes not respond to TXD[3:0],
TX-EN, and TX-ER inputs, and it presents a high impedance
on its TX-CLK, RX-CLK, RX-DV, RX-ER, D[3:0], COL, and
CRS outputs.
Re-Start Auto-Negotiation process control.
1: Auto-Negotiation process will be re-started. This bit will be
cleared by STE100P itself after the Auto-negotiation restarted.
Full/Half duplex mode select.
1: Full duplex mode is selected. This bit will be ignored if Auto-
Negotiation is enabled (bit 12 of PR0 = 1).
0: Half duplex mode is selected
Collision test control.
1: Collision test is enabled. 0: normal operation
This bit, when set, causes the COL signal to be asserted as a
result of the assertion of TX _EN. De-assertion of TX_EN will
cause the COL signal to be de-asserted.
Reserved
100BASE-T4 ability.
Always 0, since STE100P has no T4 ability.
100Base-TX full duplex ability.
Always 1, since STE100P has the 100Base-TX full duplex
ability.
100Base-TX half duplex ability.
Always 1, since STE100P has the 100Base-TX half duplex
ability.
10Base-T full duplex ability.
Always 1, since STE100P has 10Base-T full duplex ability.
10Base-T half duplex ability.
Always 1, since STE100P has 10Base-T half duplex ability.
Reserved
Descriptions
Default Val
0
0
0
0
0
0
0
1
1
1
1
0
STE100P
RW Type
R/W
R/W
R/W
R/W
R/W
RO
RO
RO
RO
RO
RO
RO
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