E-STE100P STMicroelectronics, E-STE100P Datasheet - Page 7

• Manufacturer Part Number: E-STE100P
• Description: IC TRANSCEIVER 3.3V 64 TQFP
• Manufacturer: STMicroelectronics
• Type: Transceiverr

Specifications of E-STE100P

• Number Of Drivers/receivers: 1/1
• Protocol: MII
• Voltage - Supply: 3.15 V ~ 3.45 V
• Mounting Type: Surface Mount
• Package / Case: 64-TQFP, 64-VQFP
• Number Of Receivers: 1
• Data Rate: 10/100Mbps
• Operating Supply Voltage (typ): 3.3V
• Package Type: TQFP
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.45V
• Operating Supply Voltage (min): 3.15V
• Mounting: Surface Mount
• Pin Count: 64
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-2143; STE100P

5
5.1
The Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the
LED/PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hard-
ware Control Interface provides initial values for the MDIO registers, and then passes control to the MDIO
Interface. Individual chip addressing via the LED/PAD pins allows multiple STE100P devices to share the
MII interface. Table 3 shows how to set up the desired operating configurations using the Hardware Con-
trol Interface.
Table 3. Operating Configurations / Auto-Negotiation Enabled
Note: If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated
5.2
The LED output pins can be used to drive LED’s directly, or can be used to provide status information to
a network management device. The active state of each LED output driver is dependent on the logic level
sampled by the corresponding PHY address input upon power-up/reset. For example, if a given PAD input
is resistively pulled low then the corresponding LED output will be configured as an active high driver. Con-
versely, if a given PAD input is resistively pulled high then the corresponding LED output will be configured
as an active low driver. These outputs are standard CMOS drivers and not open-drain.
The STE100P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all
zeros (00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0
bit 10.
(See Section 7 for more detailed descriptions of device operation.)
Advertise All
Advertise 100 HD
Advertise 100 HD/FD
Advertise 10 HD
Advertise 10 HD/FD
Advertise 10/100 HD
HARDWARE CONTROL INTERFACE
Operating Configurations
LED / PHY Address Interface
Configuration
in the table describing register PR4.
Desired
CFG0
1
1
1
0
1
0
Input Value
CFG1
1
0
0
1
1
1
FDE
1
0
1
0
1
0
[8] TXF
1
0
1
0
0
0
PR4 Register Bits Affected
[7] TXH
1
1
1
0
0
1
[6] 10F
1
0
0
0
1
0
STE100P
[5] 10H
1
0
0
1
1
1
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