FAN3278TMX Fairchild Semiconductor, FAN3278TMX Datasheet

MOSFET & Power Driver ICs Low-Voltage 27V PMOS NMOS Bridge Driver

FAN3278TMX

Manufacturer Part Number
FAN3278TMX
Description
MOSFET & Power Driver ICs Low-Voltage 27V PMOS NMOS Bridge Driver
Manufacturer
Fairchild Semiconductor
Datasheet

Specifications of FAN3278TMX

Product
MOSFET Gate Drivers
Rise Time
17 ns
Fall Time
8 ns
Propagation Delay Time
45 ns
Supply Voltage (max)
27 V
Supply Current
1.3 mA
Mounting Style
SMD/SMT
Package / Case
SOIC-8
Output Current
1.5 A
Output Voltage
30 V
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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© 2010 Fairchild Semiconductor Corporation
FAN3278 • Rev. 1.0.0
FAN3278
30V PMOS-NMOS Bridge Driver
Features
Applications
8V to 27V Optimum Operating Range
Drives High-Side PMOS and Low-Side NMOS in
Motor Control or Buck Step-Down Applications
Output Drive-Voltage Magnitude Limited: < 13V
for V
Biases Each Load Device OFF with a 100kΩ
Resistor when V
Low-Voltage TTL Input Thresholds
Peak Gate Drives at 12V: +1.5A Sink, -1.0A Source
Internal Resistors Hold Driver Off When
No Inputs Present
8-Lead SOIC Package
Rated from –40°C to +125°C Ambient
Motor Control with PMOS / NMOS Half-Bridge
Configuration
Buck Converters with High-Side PMOS Device;
100% Duty Cycle Operation Possible
Logic-Controlled Load Circuits with High-Side
PMOS Switch
DD
up to 30V
DD
Below Operating Level
Figure 1. Typical Application
Description
The FAN3278 dual 1.5A gate driver is optimized to drive
a high-side P-channel MOSFET and a low-side
N-channel MOSFET in motor control applications
operating from a voltage rail up to 27V. Internal circuitry
limits the voltage applied to the gates of the external
MOSFETs to 13V maximum. The driver has TTL input
thresholds and provides buffer and level translation from
logic inputs. Internal circuitry prevents the output
switching devices from operating if the V
voltage is below the IC operation level. Internal 100kΩ
resistors bias the non-inverting output LOW and the
inverting output to V
off during startup intervals when logic control signals
may not be present.
The FAN3278 driver incorporates MOSFET devices for
the final output stage, providing high current throughout
the MOSFET turn-on / turn-off transition to minimize
switching loss. The internal gate-drive regulators
provide optimum gate-drive voltage when operating
from a rail of 8V to 27V. The FAN3278 can be driven
from a voltage rail of less than 8V; however, its gate
drive current is reduced.
The FAN3278 has two independent ENABLE pins that
default to ON if not connected. If the ENABLE pin for
non-inverting channel A is pulled LOW, OUTA is forced
LOW. If the ENABLE pin for inverting channel B is
pulled LOW, OUTB is forced HIGH. If an input is left
unconnected, internal resistors bias the inputs such that
the external MOSFETs are OFF.
DD
to keep the external MOSFETs
January 2011
www.fairchildsemi.com
DD
supply

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FAN3278TMX Summary of contents

Page 1

... Buck Converters with High-Side PMOS Device; 100% Duty Cycle Operation Possible  Logic-Controlled Load Circuits with High-Side PMOS Switch © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Description The FAN3278 dual 1.5A gate driver is optimized to drive a high-side P-channel MOSFET and a low-side N-channel MOSFET in motor control applications operating from a voltage rail up to 27V ...

Page 2

... Ordering Information Part Number FAN3278TMX Non-Inverting Channel and Inverting Channel with Dual Enable Figure 2. Typical 3-Phase Blower Motor Drive Application © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Logic 2 Input Packing Threshold Method 2,500 Units on TTL Tape & Reel www.fairchildsemi.com ...

Page 3

... Gate Drive Output B (inverted from the input). Held HIGH unless the required input is present 5 OUTB and V is above the internal voltage threshold where the IC is functional VDD Supply Voltage. Provides power to the IC. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Figure 3. Pin Configuration (Top View) (1)  ( Description 3  ...

Page 4

... Note: 7. Default input signal if no external connection is made. Block Diagram V DD 100k ENA 1 INA 2 100k GND 3 INB 4 100k © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 FAN3278 (Channel B) OUTA ENB ( ( 13V LS Predriver Low-Side Drive Regulator High-Side Drive Regulator HS Predriver ...

Page 5

... Supply Voltage Range DD V Enable Voltage (ENA, ENB Input Voltage (INA, INB Operating Ambient Temperature A © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Parameter Human Body Model, JEDEC JESD22-A114 Charged Device Model, JEDEC JESD22-C101 Parameter 5 Min. Max. Unit -0.3 30.0 V GND - 0 ...

Page 6

... Propagation B Delay, EN Falling D1 Timing Diagrams 90% Output 10% Input V INH or V Enable INL t D1 Figure 5. Non-Inverting © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 =-40°C to +125°C. Currents are defined as positive into the device ( Conditions (8) INA=ENA=V DD (9) INA=ENA from from (10) (11 1V/ns Slew Rate ...

Page 7

... The FAN3278 can be driven from a voltage rail of less than 8V; however, with reduced gate drive current inputs have near-TTL thresholds (refer to the ENABLE section). 10. Not tested in production. 11. See the Timing Diagrams of Figure 5 and Figure 6. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 (Continued) =-40°C to +125°C. Currents are defined as positive into the device ( ...

Page 8

... Typical Performance Characteristics Typical characteristics are provided at T Figure 7. I (Static) vs. Supply Voltage DD Figure 9. I (No Load) vs. Frequency DD Figure 11. Input Thresholds vs. Temperature © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 =25°C and V =12V unless otherwise noted (12) Figure 8. I Figure 10 (12) (Static) vs. Temperature DD (1nF Load) vs ...

Page 9

... Note: 12. For any inverting inputs pulled LOW, non-inverting inputs pulled HIGH, or outputs driven HIGH; static I increases by the current flowing through the corresponding pull-up/down resistor, shown in Figure 4. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 =25°C and V =12V unless otherwise noted. ...

Page 10

... A. At power-up, the driver output for channel A remains LOW until V reaches the voltage where the DD device starts operating, then OUTA operates in-phase with INA. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 DD hysteresis voltage of Figure 18. Non-Inverting Startup Waveforms Figure 19 illustrates startup waveforms for inverting channel B ...

Page 11

... These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input, enable, or output leads. For © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 best results, make connections to all pins as short and direct as possible. ...

Page 12

... Table 1. Differences between FAN3278 and FAN3268 Supply Voltage Gate Drive Regulator Minimum Operating Voltage Startup Output Gate Drive Architecture OUTB Gate Drive Current Strength © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Test Circuit =43°C/ system JB would be limited J maintain the junction ...

Page 13

... FAN3122T Single 9A +9.7A / -7.1A FAN3122C Single 9A +9.7A / -7.1A Notes: 13. Typical currents with OUT at 6V and V 14. Thresholds proportional to an externally supplied reference voltage. © 2010 Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 Input (13) Threshold CMOS Single Channel of Dual-Input/Single-Output (14) ...

Page 14

... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...

Page 15

... Fairchild Semiconductor Corporation FAN3278 • Rev. 1.0.0 15 www.fairchildsemi.com ...

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