DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 56

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

5 0 Bus Interface
5 4 5 Master Mode Bus Cycles
In order to add additional compatibility with different bus
architectures there are two other modes that affect the op-
eration of the bus These modes are called the synchronous
and asynchronous modes and are programmed by setting
or resetting the SBUS bit in the Data Configuration Register
(DCR) The synchronous and asynchronous modes do not
have an effect on slave accesses to the SONIC but they do
affect the master mode operation Within the particular bus
processor mode synchronous and asynchronous modes
are very similar This section discusses all four modes of
operation of the SONIC (National Intel vs Motorola syn-
chronous vs asynchronous) when it is a bus master
In this section the rising edge of T1 and T2 means the
beginning of these states and the falling edge of T1 and T2
means the middle of these states
5 4 5 1 Adding Wait States
To accommodate different memory speeds the SONIC pro-
vides two methods for adding wait states for its bus opera-
tions Both of these methods can be used individually or in
conjunction with each other A memory cycle is extended by
adding additional T2 states The first method inserts wait-
states by withholding the assertion of DSACK0 1 STERM or
RDYi The other method allows software to program wait-
states Programming the WC0 WC1 bits in the Data Config-
uration Register allows 1 to 3 wait-states to be added on
each memory cycle These wait states are inserted between
the T1 and T2 bus states and are called T2(wait) bus states
The SONIC will not look at the DSACK0 1 STERM or RDYi
lines until the programmed wait states have passed Hence
(Continued)
56
in order to complete a bus operation that includes pro-
grammed wait states the DSACK0 1 STERM or RDYi lines
must be asserted at their proper times at the end of the
cycle during the last T2 not during a programmed wait
state The only exception to this is asynchronous mode
where DSACK0 1 or RDYi would be asserted during the last
programmed wait state T2 (wait) See the timing for these
signals in the timing diagrams for more specific information
Programmed wait states do not affect Slave Mode bus cy-
cles
5 4 5 2 Memory Cycle for BMODE
Mode
On the rising edge of T1 the SONIC asserts ECS to indicate
that the memory cycle is starting The address (A31-A1)
bus status (S2-S0) and the direction strobe (MRW) are driv-
en and do not change for the remainder of the memory
cycle On the falling edge of T1 the SONIC deasserts ECS
and asserts AS
In synchronous mode DSACK0 1 are sampled on the rising
edge of T2 T2 states will be repeated until DSACK0 1 are
sampled properly in a low state DSACK0 1 must meet the
setup and hold times with respect to the rising edge of bus
clock for proper operation
During read cycles ( Figure 5-8 ) data (D31-D0) is latched at
the falling edge of T2 and DS is asserted at the falling edge
of T1 For write cycles ( Figure 5-9 ) data is driven on the
rising edge of T1 If there are wait states inserted DS is
asserted on the falling edge of T2 DS is not asserted for
zero wait state write cycles The SONIC terminates the
memory cycle by deasserting AS and DS at the falling edge
of T2
e
1 Synchronous