DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 22

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

3 0 Buffer Management
TXpkt config to TXpkt frag size (6 accesses) For the next
fragment if any it reads the next 3 fields from TXpkt frag
ptr0 to TXpkt frag size (3 accesses) At the end of trans-
mission it writes the status information to TXpkt status and
reads the TXpkt link field (2 accesses)
3 5 3 2 Transmit Completion
The SONIC stops transmitting under two conditions In the
normal case the SONIC transmits the complete list of de-
scriptors in the TDA and stops after it detects EOL
the second case certain transmit errors cause the SONIC
to abort transmission If FIFO Underrun Byte Count Mis-
match Excessive Collision or Excessive Deferral (if en-
abled) errors occur transmission ceases The CTDA regis-
ter points to the last packet transmitted The system can
also halt transmission under software control by setting the
HTX bit in the Command register Transmission halts after
the SONIC writes to the TXpkt status field
3 5 4 Dynamically Adding TDA Descriptors
Descriptors can be dynamically added during transmission
without halting the SONIC The SONIC can also be guaran-
teed to transmit the complete list including newly appended
descriptors (barring any transmit abort conditions) by ob-
serving the following rule The last TXpkt link field must
point to the next location where a descriptor will be added
(see step 3 below and Figure 3-15 ) The procedure for ap-
pending descriptors consists of
1 Creating a new descriptor with its TXpkt link pointing to
2 Resetting the EOL bit to a ‘‘0’’ of the previously last de-
3 Re-issuing the Transmit command (setting the TXP bit in
Step 3 assures that the SONIC will transmit all the packets
in the list If the SONIC is currently transmitting the Trans-
mit command has no effect and continues transmitting until
it detects EOL
ting it continues transmitting from where it had previously
stopped
the next vacant descriptor location and its EOL bit set to
a ‘‘1’’
scriptor
the Command register)
FIGURE 3-15 Initializing Last Link Field
e
1 If the SONIC had just finished transmit-
(Continued)
TL F 10492–20
e
1 In
22
ure 4-3 shows the programmer’s model and Table 4-1 lists
4 0 SONIC Registers
The SONIC contains two sets of registers The status con-
trol registers and the CAM memory cells The status control
registers are used to configure control and monitor SONIC
operation They are directly addressable registers and occu-
py 64 consecutive address locations in the system memory
space (selected by the RA5– RA0 address pins) There are
a total of 64 status control registers divided into the follow-
ing categories
User Registers These registers are accessed by the user
to configure control and monitor SONIC operation These
are the only SONIC registers the user needs to access Fig-
the attributes of each register
Internal Use Registers These registers (Table 4-2) are
used by the SONIC during normal operation and are not
intended to be accessed by the user
National Factory Test Registers These registers (Table
4-3) are for National factory use only and should never be
accessed by the user Accessing these registers during nor-
mal operation can cause improper functioning of the
SONIC
4 1 THE CAM UNIT
The CAM unit memory cells are indirectly accessed by pro-
gramming the CAM descriptor area in system memory and
issuing the LCAM command (setting the LCAM bit in the
Control register) The CAM cells do not occupy address lo-
cations in register space and thus are not accessible
through the RA5– RA0 address pins The CAM control regis-
ters however are part of the user register set and must be
initialized before issuing the LCAM command (see Section
4 3 10)
The Content Addressable Memory (CAM) consists of six-
teen 48-bit entries for complete address filtering (Figure 4-1)
of network packets Each entry corresponds to a 48-bit des-
tination address that is user programmable and can contain
any combination of Multicast or Physical addresses Each
entry is partitioned into three 16-bit CAM cells accessible
through CAM Address Ports (CAP 2 CAP 1 and CAP 0) with
CAP0 corresponding to the least significant 16 bits of the
Destination Address and CAP2 corresponding to the most
significant bits The CAM is accessed in a two step process
First the CAM Entry Pointer is loaded to point to one of the
16 entries Then each of the CAM Address Ports is ac-
cessed to select the CAM cell The 16 user programmable
CAM entries can be masked out with the CAM Enable regis-
ter (see Section 4 3 10)
Note It is not necessary to program a broadcast address into the CAM
4 1 1 The Load CAM Command
Because the SONIC uses the CAM for a relatively long peri-
od of time during reception it can only be written to via the
CAM Descriptor Area (CDA) and is only readable when the
when it is desired to accept broadcast packets Instead to accept
broadcast packets set the BRD bit in the Receive Control register If
the BRD bit has been set the CAM is still active This means that it is
possible to accept broadcast packets at the same time as accepting
packets that match physical addresses in the CAM