DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 47

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

NETWORK INTERFACE PINS (Continued)
BUS INTERFACE PINS
LBK
EXUSR2
PCOMP
SEL
PREJ
OSCOUT
OSCIN
BMODE
5 0 Bus Interface
Symbol
Driver
Type
TRI
TRI
TP
TP
Direction
(Continued)
O Z
O Z
O
O
I
I
I
I
This pin will be TRI-STATE until the DCR has been written to (See Section 4 3 2
EXBUS for more information )
Loopback (LBK) When ENDEC loopback is programmed LBK is asserted high
Although this signal is used internally by the SONIC it is also provided as an output to
the user
Extended User Output (EXUSR2) When EXBUS has been set (see Section 4 3 2) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 4 3 7)
Packet Compression This pin is used with the Management Bus of the DP83950
Repeater Interface Controller (RIC) The SONIC can be programmed to assert PCOMP
whenever there is a CAM match or when there is not a match The RIC uses this signal
to compress (shorten) a received packet for management purposes and to reduce
memory usage (See the DP83950 datasheet for more details on the RIC Management
Bus ) The operation of this pin is controlled by bits 1 and 2 in the DCR2 register PCOMP
will remain TRI-STATE until these bits are written to This signal is asserted right after
the 4th bit of the 7th byte of the incoming packet and is deasserted one transmit clock
(TXC) after CRS is driven low
Mode Select (EXT
TX
interface When tied to V
to ground the voltage at TX
side of the isolation transformer ( Figure 6-2 )
Packet Reject This signal is used to reject received packets When asserted low for at
least two receive clocks (RXC) the SONIC will reject the incoming packet This pin can
be asserted up to the 2nd to the last bit of reception to reject a packet
Crystal Feedback Output This signal is used to provide clocking signals for the
internal ENDEC A crystal can be connected to this pin along with OSCIN See Section
6 1 3 for more information about using oscillators or crystals
Crystal Feedback Input or External Oscillator Input This signal is used to provide
clocking signals for the internal ENDEC A crystal may be connected to this pin along
with OSCOUT or an oscillator module may be used Typically the output of an oscillator
module is connected to this pin See Section 6 1 3 for more information about using
oscillator modules or crystals
Bus Mode This input enables the SONIC to be compatible with standard
microprocessor buses The level of this pin affects byte ordering (little or big endian) and
controls the operation of the bus interface control signals A high level (tied to V
selects Motorola mode (big endian) and a low level (tied to ground) selects National
Intel mode (little endian) Note the alternate pin definitions for AS ADS MRW MWR
INT INT BR HOLD BG HLDA SRW SWR DSACK0 RDYo and DSACK1 RDYi
TABLE 5-1 Pin Description (Continued)
a
and TX
b
during idle at the primary of the isolation transformer on the network
e
47
0) This pin is used to determine the voltage relationship between
CC
a
TX
is positive with respect to TX
a
and TX
Description
b
are at equal voltages during idle When tied
b
during idle on the primary
CC
)