DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 46

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

NETWORK INTERFACE PINS (Continued)
RXDo
RXDi
EXUSR0
RXCo
RXCi
EXUSR1
TXD
EXUSR3
TXE
TXCo
TXCi
STERM
5 0 Bus Interface
Symbol
Driver
Type
TRI
TRI
TRI
TRI
TP
TP
TP
TP
Direction
(Continued)
O Z
O Z
O Z
O Z
O
O
O
O
I
I
I
I
This pin will be TRI-STATE until the DCR has been written to (See Section 4 3 2
EXBUS for more information )
Receive Data Output (RXDo) from the internal ENDEC (EXT
When EXT
MAC units This signal must be sampled on the rising edge of the receive clock output
(RXCo) Although this signal is used internally by the SONIC it is also provided as an
output to the user
Receive Data Input (RXDi) from an external ENDEC (EXT
decoded from the external ENDEC This data is clocked in on the rising edge of RXCi
Extended User Output (EXUSR0) When EXBUS has been set (see Section 4 3 2) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 4 3 7)
This pin will be TRI-STATE until the DCR has been written to (See Section 4 3 2
EXBUS for more information )
Receive Clock Output (RXCo) from the internal ENDEC (EXT
the RXCo signal is internally connected between the ENDEC and MAC units This signal
is the separated receive clock from the Manchester data stream It remains active 5-bit
times after the deassertion of CRSo Although this signal is used internally by the
SONIC it is also provided as an output to the user
Receive Clock Input (RXCi) from an external ENDEC (EXT
received clock from the Manchester data stream This signal is generated from an
external ENDEC
Extended User Output (EXUSR1) When EXBUS has been set (see Section 4 3 2) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 4 3 7)
This pin will be TRI-STATE until the DCR has been written to (See Section 4 3 2
EXBUS for more information )
Transmit Data (TXD) The serial NRZ data from the MAC unit which is to be decoded
by an external ENDEC Data is valid on the rising edge of TXC Although this signal is
used internally by the SONIC it is also provided as an output to the user
Extended User Output (EXUSR3) When EXBUS has been set (see Section 4 3 2) this
pin becomes a programmable output It will remain TRI-STATE until the SONIC
becomes a bus master at which time it will be driven according to the value
programmed in the DCR2 (Section 4 3 7)
Transmit Enable This pin is driven high when the SONIC begins transmission and
remains active until the last byte is transmitted Although this signal is used internally by
the SONIC it is also provided as an output to the user
This pin will be TRI-STATE until the DCR has been written to (See Section 4 3 2
EXBUS for more information )
Transmit Clock Output (TXCo) from the internal ENDEC (EXT
clock transmit clock output is derived from the 20 MHz oscillator When EXT
TXCOUT signal is internally connected between the ENDEC and MAC units Although
this signal is used internally by the SONIC it is also provided as an output to the user
Transmit Clock Input (TXCi) (EXT
used for shifting data out of the MAC unit serializer This clock is nominally 10 MHz
Synchronous Termination (STERM) When the SONIC is a bus master it samples this
pin before terminating its memory cycle This pin is sampled synchronously and may
only be used in asynchronous bus mode when BMODE
details
TABLE 5-1 Pin Description (Continued)
e
0 the RXDOUT signal is internally connected between the ENDEC and
46
e
Description
1) This input clock from an external ENDEC is
e
1 See Section 5 4 5 for more
e
e
e
1) The NRZ data
e
1) The separated
e
0) NRZ data output
0) When EXT
0) This 10 MHz
e
0 the
e
0