DP83932CVF-20 National Semiconductor, DP83932CVF-20 Datasheet - Page 29

• Manufacturer Part Number: DP83932CVF-20
• Description: IC CTRLR ORIENT NETWORK 132PQFP
• Manufacturer: National Semiconductor
• Series: SONIC™r

Specifications of DP83932CVF-20

• Controller Type: Ethernet Network Interface Controller
• Interface: Bus
• Voltage - Supply: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-MQFP, 132-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Supply: -
• Operating Temperature: -
• Other names: *DP83932CVF-20

12 11
4 0 SONIC Registers
4 3 2 Data Configuration Register
(RA
This register (Figure 4-5) establishes the bus cycle options for reading writing data to from 16- or 32-bit memory systems
During a hardware reset bits 15 and 13 are cleared all other bits are unaffected (Because of this the first thing the driver
software does to the SONIC should be to set up this register ) All bits are unaffected by a software reset This register must only
be accessed when the SONIC is in reset mode (i e the RST bit is set in the Command register)
Bits
15
14
13
k
r w
EXBUS
5 0
r w
15
e
read write
l
EXBUS EXTENDED BUS MODE
Setting this bit enables the Extended Bus mode which enables the following
1)Extended Programmable Outputs EXUSR
2)Synchronous Termination STERM This changes the TXC pin from the External ENDEC interface into a
3)Asynchronous Bus Retry Causes BRT to be clocked in asynchronously off the falling edge of bus clock This only
Must be 0
LBR LATCHED BUS RETRY
The LBR bit controls the mode of operation of the BRT signal (see pin description) It allows the BUS Retry operation
to be latched or unlatched
0 Unlatched mode The assertion of BRT forces the SONIC to finish the current DMA operation and get off the bus
1 Latched mode The assertion of BRT forces the SONIC to finish the current DMA operation as above however the
Note Unless LBR is set to a ‘‘1’’ BRT must remain asserted at least until the SONIC has gone idle See Section 5 4 6 and the timing for Bus Retry
PO1 PO0 PROGRAMMABLE OUTPUTS
The PO1 PO0 bits individually control the USR1 0 pins respectively when SONIC is a bus master (HLDA or BGACK is
active) When PO1 PO0 are set to a 1 the USR1 USR0 pins are high during bus master operations and when these
bits are set to a 0 the USR1 USR0 pins are low during bus master operations
e
external ENDEC interface into four programmable user outputs EXUSR
USR
these four pins will be TRI-STATE and will remain that way until the DCR is changed If EXBUS is enabled then
these pins will remain TRI-STATE until the SONIC becomes a bus master at which time they will be driven according
to the DCR2 If EXBUS is disabled then these four pins work normally as external ENDEC interface pins
synchronous memory termination input for compatibility with Motorola style processors This input is only useful
when Asynchronous Bus mode is selected (bit 10 below is set to ‘‘0’’) and BMODE
hardware reset this pin will be TRI-STATE and will remain that way until the DCR is changed If EXBUS is enabled
this pin will remain TRI-STATE until the SONIC becomes a bus master at which time it will become the STERM
input If EXBUS is disabled then this pin works normally as the TXC pin for the external ENDEC interface
applies however when the SONIC is operating in asynchronous mode (bit 10 below is set to ‘‘0’’) If EXBUS is not
set XTO (BRT) is sampled synchronously off the rising edge of bus clock (See Section 5 4 6 )
The SONIC will retry the operation when BRT is deserted
SONIC will not retry until BRT is deasserted the BR bit in the ISR (see Section 4 3 6) has been reset and BRT is
deasserted Hence the mode has been latched on until the BR bit is cleared
14
1h)
0
in section 7 0
k
1 0
LBR
r w
13
l
These outputs are programed with bits 15-12 in the DCR2 (see Section 4 3 7) On hardware reset
PO1
r w
12
(Continued)
PO0 SBUS USR1 USR0 WC1
r w
EXBUS
LBR
PO0 PO1
SBUS
USR0 USR1
WC0 WC1
DW
BMS
RFT0 RFT1
TFT0 TFT1
11
Field
FIGURE 4-5 Data Configuration Register
r w
10
r w
9
EXTENDED BUS MODE
LATCHED BUS RETRY
PROGRAMMABLE OUTPUTS
SYNCHRONOUS BUS MODE
USER DEFINABLE PINS
WAIT STATE CONTROL
DATA WIDTH SELECT
BLOCK MODE SELECT FOR DMA
RECEIVE FIFO THRESHOLD
TRANSMIT FIFO THRESHOLD
k
3 0
r w
8
l
29
Description
This changes the TXD LBK RXC and RXD pins from the
r w
7
Meaning
WC0
r w
6
DW
r w
5
k
3 0
BMS RFT1 RFT0 TFT1 TFT0
r w
4
l
respectively which are similar to
r w
e
3
1 (Motorola mode) On
r w
2
r w
1
r w
0