DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 46

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

6 0 Operation of AT LANTIC Controller
Ring not yet read by the host If the local DMA address ever
reaches the Boundary reception is aborted The Boundary
Pointer is also used to initialize the Remote DMA for remov-
ing a packet and is advanced when a packet is removed A
simple analogy to remember the function of these registers
is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer
Note 1 At initialization the Page Start Register value should be loaded into
Note 2 The Page Start Register mut not be initalized to 00H
Beginning of Reception
When the first packet begins arriving the AT LANTIC Con-
troller begins storing the packet at the location pointed to by
the Current Page Register An offset of 4 bytes is saved in
this first buffer to allow room for storing receive status corre-
sponding to this packet
Linking Receive Buffer Pages
If the length of the packet exhausts the first 256 byte buffer
the DMA performs a forward link to the next buffer to store
the remainder of the packet For a maximal length packet
the buffer logic will link six buffers to store the entire packet
Buffers cannot be skipped when linking a packet will always
be stored in contiguous buffers Before the next buffer can
be linked the Buffer Management Logic performs two con-
parisons The first comparison tests for equality between
the DMA address of the next buffer and the contents of the
Page Stop Register If the buffer address equals the Page
Stop Register the buffer management logic will restore the
DMA to the first buffer in the Receive Buffer Ring value
programmed in the Page Start Address Register The sec-
ond comparison tests for equality between the DMA ad-
dress of the next buffer address and the contents of the
Boundary Pointer Register If the two values are equal the
reception is aborted The Boundary Pointer Register can be
used to protect against overwriting any area in the receive
buffer ring that has not yet been read When linking buffers
buffer management will never cross this pointer effectively
avoiding any overwrites If the buffer address does not
match either the Boundary Pointer or Page Stop Address
the link to the next buffer is performed
FIGURE 30 Received Packet Enters the Buffer Pages
both the Current Page Register and the Boundary Pointer Register
TL F 11498–27
46
(Continued)
Linking Buffers
Before the DMA can enter the next contiguous 256 byte
buffer the address is checked for equality to PSTOP and to
the Boundary Pointer If neither are reached the DMA is
allowed to use the next buffer
Buffer Ring Overflow
If the Buffer Ring has been filled and the DMA reaches the
Boundary Pointer Address reception of the incoming pack-
et will be aborted by the AT LANTIC Controller Thus the
packets previously received and still contained in the Ring
will not be destroyed
In heavily loaded networks which cause overflows of the
Receive Buffer Ring the AT LANTIC Controller may disable
the local DMA and suspend further receptions even if the
Boundary register is advanced beyond the Current register
In the event that the AT LANTIC Controller should encoun-
ter a receive buffer overflow it is necessary to implement
the following routine A receive buffer overflow is indicated
by the AT LANTIC Controller’s assertion of the overflow bit
(OVW) in the Interrupt Status Register (ISR)
If this routine is not adhered to the AT LANTIC Controller
may act in an unpredictable manner It should also be noted
that it is not permissible to service an overflow interrupt by
continuing to empty packets from the receive buffer without
implementing the prescribed overflow routine A flow chart
of the AT LANTIC
found in Figure 32
Note It is necessary to define a variable in the driver which will be called
1 Read and store the value of the TXP bit in the AT LAN-
2 Issue the STOP command to the AT LANTIC Controller
3 Wait for at least 1 6 ms Since the AT LANTIC Controller
TIC Controller’s Command Register
This is accomplished by setting the STP bit in the
AT LANTIC Controller’s Command Register Writing 21
H to the Command Register will stop the AT LANTIC
Controller
will complete any transmission or reception that is in
progress it is necessary to time out for the maximum
possible duration of an Ethernet transmission or recep-
tion By waiting 1 6 ms this is achieved with some guard
band added Previously it was recommended that the
RST bit of the Interrupt Status Register be polled to in-
sure that the pending transmission or reception is com-
pleted This bit is not a reliable indicator and subsequent-
ly should be ignored
‘‘Resend’’
FIGURE 31 Linking Receive Buffer Pages
TM
Controller’s overflow routine can be
TL F 11498 – 28