DP83905AVQB National Semiconductor, DP83905AVQB Datasheet - Page 13

• Manufacturer Part Number: DP83905AVQB
• Description: IC CONTROLR AT/LAN TP IN 160PQFP
• Manufacturer: National Semiconductor
• Series: AT/LANTIC™r

Specifications of DP83905AVQB

• Controller Type: AT, LAN Twisted-Pair Interface Controller
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 100mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 160-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Interface: -
• Other names: *DP83905AVQB

Figure 9 shows how the RESET circuitry operates
10
4 0 Functional Description
4 2 POWER ON RESET OPERATION
The AT LANTIC Controller configures itself after a Reset
signal is applied To be recognized as a valid Power-On-Re-
set the Reset signal must be active for at least 415
The ISA standard determines that within 500 ns of RESET
going active all devices should enter the appropriate reset
condition The AT LANTIC Controller will generate the inter-
nal signal IOinactive after RESET has been active for
415 ns which will disable all outputs and cause RESET to
be the only input monitored The AT LANTIC Controller will
not respond to a RESET pulse of shorter duration than this
An internal timer continues to monitor the amount of time
RESET is active After 415 s it is considered a valid Power-
On-Reset and an internal signal called RegLoad is generat-
ed
When a Power-On-Reset occurs the AT LANTIC Controller
latches in the values on the configuration pins and uses
these to configure the internal registers and options Inter-
nally these pins contain pull-down resistors which are en-
abled when IOinactive goes active If any pins are uncon-
nected they default to a logic zero The internal pull-down
resistor has a high resistance to allow the external pull-up
resistors to be of a high value This limits the current taken
by the memory support bus The suggested external resistor
value is 10 k
the memory support bus when RESET goes inactive if Reg-
Load is active The internal pull-down resistors are enabled
onto the bus until RegLoad has gone inactive
A Power-On-Reset also causes the AT LANTIC Controller
to load the internal PROM store from the EEPROM which
can take up to 320 s This occurs after RegLoad has gone
inactive The AT LANTIC Controller will be inaccessible dur-
ing this time If EECONFIG is held high the configuration
data loaded on the falling edge of RESET will be overwritten
with data read from the serial EEPROM Regardless of the
level on EECONFIG the PROM store will always be loaded
with data from the serial EEPROM during the time specified
as EELoad
4 3 EEPROM OPERATION
The AT LANTIC Controller uses an NM93C06
EEPROM with compatible timings The NM93C06 is a 256-
bit device arranged as 16 words each 16 bits wide The
programmed contents of the EEPROM is shown in Figure
Mapping EEPROM Into PROM Space
Data is read from the EEPROM at boot time and stored in
registers within the AT LANTIC Controller While this opera-
tion takes place the AT LANTIC Controller can not be ac-
FIGURE 9 RESET Operation
The configuration registers are loaded from
(Continued)
TL F 11498 – 7
or
s
13
Note 1 The contents of locations 03H and 04H differ between I O Mode
and Shared Memory Mode The Shared Memory Mode values are shown in
parentheses For compatibility with both modes default to the shared memo-
ry mode values
Note 2 Programming 73H into the upper address is not absolutely required
but is strongly recommended for future compatibility of manufacturing pro-
cess
cessed by the system These registers are mapped into the
space traditionally occupied by the PROM in the NE2000 or
the EtherCard PLUS16 The size and format of this data
read is determined by the mode of operation
SHARED MEMORY MODE
In this mode program the EEPROM to contain the node’s
Ethernet address in the first six bytes a byte identifying the
type of board AT LANTIC Controller is emulating in byte 7
and a checksum byte in byte 8 The two’s complement sum
of these eight bytes should equal FFH
In this Mode the AT LANTIC Controller reads the first 4
words from the EEPROM and maps them into the I O map
at the appropriate address
I O PORT MODE
In this mode program the EEPROM to contain the node’s
Ethernet address in the first six bytes The user should then
program 5757H and 4242H into the subsequent bytes The
AT LANTIC Controller will decide which of these values
should be loaded into the PROM store depending on the
DWlD pin (The data width is programmed in this mode by
setting the WTS bit in the Data Configuration Register and
setting the DWlD pin for the proper mode ) If some other
numerical values are preferred to indicate the mode then
they can be programmed at this location in the EEPROM
and AT LANTIC Controller will put them at the correct ad-
dress
In this mode the AT LANTIC Controller reads the first 7
words from the EEPROM and maps them into the memory
map at the appropriate address If in 16-bit mode it also
0EH
0FH
08H
07H
03H
02H E’net Address 5 E’net Address 4
01H E’net Address 3 E’net Address 2
00H E’net Address 1 E’net Address 0
FIGURE 10 EEPROM Programming Map
D15
(Checksum)
Reserved
Config B
73H
42H
57H
(Board Type)
Reserved
Config C
Config A
42H
57H
D0