TDA8026ET/C2,518 NXP Semiconductors, TDA8026ET/C2,518 Datasheet - Page 28

• Manufacturer Part Number: TDA8026ET/C2,518
• Description: IC SMART CARD SLOT 64TFBGA
• Manufacturer: NXP Semiconductors

Specifications of TDA8026ET/C2,518

• Controller Type: Smart Card Interface
• Interface: I²C
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 210mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TDA8026_1
Product data sheet
8.5.4.10 Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address
8.5.4.11 Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4
8.5.4.8 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
8.5.4.9 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
8.5.5 Selection of asynchronous or synchronous mode
04h) and card slot 5 (address 05h) bit allocation
Table 28.
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Table 29.
04h) and card slot 5 (address 05h) bit allocation
Table 30.
(address 04h) and card slot 5 (address 05h) read/write mode bit descriptions
Table 31.
When the activation sequence starts, the selected card slot on the TDA8026 uses the
RSTIN bit value to configure itself for use with asynchronous or synchronous cards. If the
RSTIN bit is set to logic 1 at the activation sequence start (the START bit changes from
LOW to HIGH), the TDA8026 will manage asynchronous cards.
In asynchronous mode, the card slot RST
counter (see
In synchronous mode, the card slot RST
bit. The card clock configuration is set by the PWDN bit value at the activation sequence
start of the selected card slot (the START bit changed from LOW to HIGH).
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Bit
7 to 0
Symbol
C[15:8]
Symbol
C[7:0]
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) read/write mode bit descriptions
Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address
04h) and card slot 5 (address 05h) bit allocation
Bank 1: Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4
(address 04h) and card slot 5 (address 05h) read/write mode bit descriptions
Section 8.9 on page
7
7
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 9 March 2010
6
6
Description
most significant byte of a programmable 16-bit clock counter. This value
applies to all slots. The reset value is A4h. See ATR
“Answer to reset counters” on page 35
Description
least significant byte of a programmable 16-bit clock counter. This value
applies to all slots. The reset value is 74h. See
5
5
35).
(n)
(n)
pin is controlled by the corresponding RSTIN
4
4
pin is controlled by the corresponding ATR
C[15:8]
C[7:0]
R/W
R/W
Multiple smart card slot interface IC
3
3
2
2
Section 8.9 on page 35
TDA8026
© NXP B.V. 2010. All rights reserved.
Section 8.9
1
1
28 of 59
0
0