TDA8026ET/C2,518 NXP Semiconductors, TDA8026ET/C2,518 Datasheet - Page 13

• Manufacturer Part Number: TDA8026ET/C2,518
• Description: IC SMART CARD SLOT 64TFBGA
• Manufacturer: NXP Semiconductors

Specifications of TDA8026ET/C2,518

• Controller Type: Smart Card Interface
• Interface: I²C
• Voltage - Supply: 2.7 V ~ 5.5 V
• Current - Supply: 210mA
• Operating Temperature: -25°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TFBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
TDA8026_1
Product data sheet
8.4.1 I
8.4.2 Bus conditions
8.4.3 Data transfer
8.4 I
Remark: Refer to the I
The I
(100 kHz) or Fast mode (400 kHz). In addition, it integrates shift register functions, shift
timing generation and slave address recognition.
The I
modules. The serial bus consists of two bidirectional lines: one for data signals (SDA) and
one for clock signals (SCL). Both the SDA and SCL lines must be connected to the
V
details).
The I
The following bus conditions are defined.
Bus not busy — Both data and clock lines remain HIGH.
Start data transfer — The START condition is generated when the state of the data line
changes from HIGH to LOW while the clock line is HIGH.
Stop data transfer — The STOP condition is generated when the state of the data line
changes from LOW to HIGH while the clock line is HIGH.
Data valid — The data line state represents valid data, after a START condition with the
data line stable for the duration of the clock signal HIGH period. There is one clock pulse
per bit of data.
Each data transfer is triggered by a START condition and finished by a STOP condition
(see
Data transfers can be performed in Standard mode at 100 kHz or Fast mode at 400 kHz.
Data transfer is performed on a byte for byte basis in both read or write modes. The
information is transmitted in bytes and each receiver acknowledges with a 9
(acknowledge).
Each byte is followed by an acknowledge bit and the transmitter must release the SDA line
during the acknowledge bit. The master generates an extra acknowledge related clock
pulse. The addressed slave receiver must generate an acknowledge bit after receiving
each byte. The master-receiver must generate an acknowledge bit after receiving each
byte clocked out of the slave transmitter.
The acknowledging device must pull-down the SDA line during the acknowledge clock
pulse to ensure the SDA line is stable LOW during the acknowledge related clock pulse
HIGH period.
2
2
DD(INTF)
•
•
C-bus protocol
C-bus description
Data transfer can only be initialized when the I
During data transfer, the data line must remain stable when the clock line is HIGH.
Changes in the data line while the clock line is HIGH are interpreted as control
signals.
Figure 13
2
2
2
C-bus interface in the TDA8026 is an I
C-bus protocol is based on bidirectional, 2-line communication between ICs or
C-bus protocol is defined as follows:
supply voltage using a pull-up resistor (refer to the I
for timing information).
All information provided in this document is subject to legal disclaimers.
2
C-bus specification for more information.
Rev. 1 — 9 March 2010
2
C-bus slave operating either Standard mode
2
Multiple smart card slot interface IC
C-bus is not busy.
2
C-bus specification for more
TDA8026
© NXP B.V. 2010. All rights reserved.
th
bit
13 of 59