TDA8026ET/C2,518 NXP Semiconductors, TDA8026ET/C2,518 Datasheet
TDA8026ET/C2,518
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TDA8026ET/C2,518 Summary of contents
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TDA8026 Multiple smart card slot interface IC Rev. 1 — 9 March 2010 1. General description The TDA8026 is a cost-effective, analog interface for addressing multiple smart card slots in a Point Of Sales (POS) terminal. It can address up ...
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... NXP Semiconductors I RST programmable clock pulse counter on asynchronous cards register on synchronous cards I ISO 7816-3 and EMV 4.2 payment systems compatibility I V DD(INTF) microcontroller and circuit; threshold internally fixed or set using an external resistor bridge deactivation at power-off; threshold internally fixed I Card presence input with a 17.8 ms (typical) built-in debouncing system on card slots ...
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... NXP Semiconductors Table 1. Quick reference data 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter Card supply voltage pins: V CC(1) V supply voltage CC V peak-to-peak ripple ripple(p-p) voltage I supply current CC General t deactivation time ...
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... NXP Semiconductors 6. Block diagram DD(INTF PORADJ MANAGEMENT B8 DCDC_OFF A5 SDWNN V DD(INTF SCL C2 SDA E2 IRQN INTAUXN INTERFACE C4 I/OUC1 CONTROL C5 I/OUC2 C3 CLKIN1 B3 CLKIN2 H1 SPRES A3 TESTMODE H7 INHIB D1 STAP5 STAP4 Fig 1. TDA8026 Block diagram TDA8026_1 Product data sheet V DD(INTREGD) GNDP POWER STEP UP UNIT CONVERTER TDA8026 AND ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. Table 3. Ball position 1 A TST2 B STAP3 C STAP4 D STAP5 ( (1) H SPRES PRES [1] The numbers in subscript and between brackets “ [2] The ball positions are those when the TDA8026 is viewed from the top. TDA8026_1 Product data sheet ...
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... NXP Semiconductors 7.2 Pin description Table 4. Symbol IRQN INTAUXN SDWNN V DD(INTF) SDA SCL A0 SPRES CLKIN1 CLKIN2 GND1 I/OUC1 I/OUC2 V CC(1) RST (1) CLK (1) C4 (1) C8 (1) I/O (1) GNDC (1) PRES (1) V CC(2) RST (2) CLK (2) I/O (2) GNDC (2) PRES (2) GNDS V CC(3) RST (3) CLK (3) I/O (3) TDA8026_1 Product data sheet ...
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... NXP Semiconductors Table 4. Symbol V CC(4) RST (4) CLK (4) I/O (4) V CC(5) RST (5) CLK (5) I/O (5) TST1 TST2 STAP3 STAP4 STAP5 n.c. PORADJ GNDP V DD(INTREGD) DCDC_OFF INHIB TESTMODE GND2 GND3 GND4 GND5 GND6 GND7 GND8 GND9 GND10 [ Input Output Power Ground Configuration. [2] Refer to the Application note AN10724 for further information. ...
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... NXP Semiconductors 8. Functional description Remark: Throughout this document ISO 7816-3 and EMV standard terminology conventions have been adhered to and it is assumed that the reader is familiar with these. 8.1 Power supplies The TDA8026 supply pins are V • • V DD(INTF) The V DD sequence. All interface signals to the system controller are referenced to the V ...
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... NXP Semiconductors 8.2.1 Standby mode In Standby mode, both the supply voltages V specification limits as described in converter is not running and the card slots are not activated. 8.2.2 Active mode In active mode, both the V within the specification limits as described in slot is activated. All card slots can be activated at once and communication performed with up to two cards slots ...
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... NXP Semiconductors • I/OUC1 and I/OUC2 are set to high-impedance. Fig 4. 8.2.4.2 Exiting shutdown mode The TDA8026 performs the following steps when exiting shutdown mode: 1. Card insertion on card slot 1 is signalled by the IRQN pin signal being driven LOW. 2. Using the IRQN pin signal, the microcontroller detects the card insertion and drives the SDWNN pin HIGH to wake-up the TDA8026 3 ...
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... NXP Semiconductors 8.3 Voltage supervisors 8.3.1 Block diagram Fig 6. 8.3.2 Description The voltage supervisor can be used to perform Power-On Resets (POR) and supply drop detection during a card session. The supervisors control the internal regulated supply voltage (V ensure problem-free operation of the TDA8026. This block controls: • ...
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... NXP Semiconductors V V DD(INTREGD) ALARMN (internal signal) Fig 8. Remark: Refer to the Application note AN10724 for further information. 8.3.3 V DD(INTREGD) An alarm signal is triggered and the analog controller resets the TDA8026 when: • V DD(INTREGD) • Pin PORADJ monitoring V The alarm is reset and the TDA8026 leaves reset mode 8 ms after V ...
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... NXP Semiconductors 2 8.4 I C-bus description Remark: Refer to the I 2 The I C-bus interface in the TDA8026 (100 kHz) or Fast mode (400 kHz). In addition, it integrates shift register functions, shift timing generation and slave address recognition. 2 8.4.1 I C-bus protocol 2 The I C-bus protocol is based on bidirectional, 2-line communication between ICs or modules ...
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... NXP Semiconductors In addition, the set-up and hold times must be taken into account. The master-receiver must signal the end of the last data byte to the slave transmitter by not sending an acknowledge bit on the last byte that has been clocked out of the slave. The transmitter must ensure the data line is HIGH to enable the master to generate the STOP condition ...
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... NXP Semiconductors 8.5 Banks and registers The device registers enable the microcontroller to control the TDA8026. These registers are defined as banks: • Bank 0 register is a read/write register which enables selection of the required card slot number and access to the corresponding registers Bank 1 registers. In addition, Bank 0 is used to write information about the interrupt status and the product version ...
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Register overview Table 7. Register overview Page number/ Register R/W Bit definition register name Bit 7 Subaddress [1] (Hex) Bank 0: Card slot selection, product version and interrupt registers (see -/48h CSb R/W Bank 1: Card slot registers (see ...
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Table 7. Register overview …continued Page number/ Register R/W Bit definition register name Bit 7 Subaddress [1] (Hex) Slot 4 04h/40h Register0 R ACTIVE 04h/40h Register0 W VCC1V8 [3] [2] 04h/42h Register1 R/W - [4] 04h/42h Register1 R/W [5] 04h/42h ...
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... NXP Semiconductors 8.5.2 Bank 0 register description The device registers enable the microcontroller to control the TDA8026. The registers are organized in bank pages to ensure compatibility with the TDA8023. Bank 0 write register enables selection of the card slot number and access to the corresponding registers in bank 1. The card slot registers in bank 1 are accessed using the confi ...
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... NXP Semiconductors 8.5.3.2 Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) read mode bit descriptions Table 11. Bit [1] f clk(ext) TDA8026_1 Product data sheet Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) read mode bit descriptions ...
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... NXP Semiconductors 8.5.3.3 Bank 1 Register0 card slot 1 (address 01h) and card slot 2 (address 02h) write mode bit descriptions Table 12. Bit [1] This bit cannot be written when the START bit is logic 1. [ mandatory condition for card slots that only one card slot I/O line is enabled at a time. When switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card slot is enabled ...
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... NXP Semiconductors 8.5.3.4 Bank 1 CSb[7:0] Register0 (address 42h) card slots 1 and card slot 2 bit allocation Table 13. Bit Card slot 1 (address 01h) and Card slot 2 (address 02h) Card Slot 1 Reg[1:0] = 00; see Symbol Access Card Slot 2 Reg[1:0] = 00; see Symbol Access Card Slot 1 and card slot 2 Reg[1:0] = 01; see ...
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... NXP Semiconductors Table 14. Bit [1] Only for card slot 2 register. [2] Only for card slot 1 register. [3] f clk(ext) 8.5.3.6 Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2 (address 02h) bit allocation Table 15. Bit Symbol Access TDA8026_1 Product data sheet Bank 1 Register1 (REG[1:0] = 00) card slot 1 (address 01h) and card slot 2 ...
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... NXP Semiconductors 8.5.3.7 Bank 1 Register1 (REG[1:0] = 01) card slot 1 (address 01h) and card slot 2 (address 02h) read/write mode bit descriptions Table 16. Bit 8.5.3.8 Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2 (address 02h) bit allocation Table 17. Bit Symbol Access 8.5.3.9 Bank 1 Register1 (REG[1:0] = 10) card slot 1 (address 01h) and card slot 2 (address 02h) read/write mode bit descriptions Table 18 ...
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... NXP Semiconductors 8.5.4 Card slots register descriptions 8.5.4.1 Bank 1 CSb[7:0] Register0 (address 40h) card slots bit allocation Table 21. Bit Card slot 3 (address 03h), Card slot 4 (address 04h) and Card slot 5 (address 05h) Symbol Access Symbol Access [1] Reserved bit position. [2] See table information on write mode bits ...
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... NXP Semiconductors 8.5.4.3 Bank 1 Register0 card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) write mode bit descriptions Table 23. Bit [1] This bit cannot be written when START bit is logic 1. [ mandatory condition for card slots that only one card slot I/O line is enabled at a time. When switching from one slot to another, the enabled I/O must be disabled before the I/O line for the required card slot is enabled ...
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... NXP Semiconductors 8.5.4.4 Bank 1 CSb[7:0] Register1 (address 42h) card slots 3 and 5 bit allocation Table 24. Bit Card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) Reg[1: Symbol Access Reg[1: Symbol Access Reg[1: Symbol Access Reg[1: Symbol Access [1] Reserved bit position. ...
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... NXP Semiconductors Table 25. Bit 8.5.4.6 Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation Table 26. Bit Symbol Access 8.5.4.7 Bank 1 Register1 (REG[1:0] = 01) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions Table 27 ...
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... NXP Semiconductors 8.5.4.8 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation Table 28. Bit Symbol Access 8.5.4.9 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions Table 29 ...
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... NXP Semiconductors • If the PDWN bit is set to logic 0 at the start of the activation, the card clock value is the CLKIN1 pin frequency for card slot 1 and the CLKIN2 pin frequency for card slots CLKDIV[1:0] = 00, the first four clock cycles are not transferred to CLK When CLKDIV[1: 11, the fi ...
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... NXP Semiconductors 8.5.6 General registers 8.5.6.1 Bank 1 General registers (address: 40h, 42h; CSb[7:0] = 00h, 06h) bit allocation Table 34. Bit Address 40h; CSb[7:0] = 00h, see Symbol Access Address 40h; CSb[7:0] = 06h Symbol Access Address 42h; CSb[7:0] = 00h Symbol Access [1] Reserved bit position. ...
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... NXP Semiconductors 8.5.6.3 Bank 1 Interrupt register (address 42h; CSb[7:0] = 00h) read mode bit descriptions Table 36. Bit [1] The INTx numbers do not match the bit positions and are as follows: bit 4 = INT5, bit 3 = INT4, bit 2 = INT3, bit 1 = INT2 and bit 0 = INT1 8.5.6.4 Bank 1 Slew rate register (address 40h; CSb[7:0] = 06h) read/write mode bit descriptions Table 37 ...
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... NXP Semiconductors 8.6 DC-to-DC converter The DC-to-DC converter has been designed to provide an average of 5 the programmable voltage regulators ( and 1.8 V) for the card slots capable of delivering a total DC current of 116 mA to the card slots. If the total current from all card slots exceeds 170 mA, the overcurrent/overload protection deactivates the DC-to-DC converter ...
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... NXP Semiconductors Card slot 1 or card slot 2 can only be activated if a card is detected as present in the slot and if an alarm is not triggered by the voltage supervisor. When both of these parameters are met, the card slots can be activated by setting the Command register START bit. The activation sequence is described in Card slots not have presence monitoring ...
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... NXP Semiconductors internal clock internal DC-to-DC converter enable Fig 10. The card slot activation sequence In Figure 10 converter remains active. 8.8.3 Deactivation sequence When the session finishes, the microcontroller resets the START bit to logic 0 and the following deactivation sequence is performed: • Card reset: RST • ...
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... NXP Semiconductors internal DC-to-DC converter enable internal clock Fig 11. Deactivation sequence In Figure 11 converter is still active. 8.9 Answer to reset counters Each TDA8026 card slot has its own sequencer. The sequencer controls the activation and deactivation sequences. In addition to these sequencers, there are two Answer To Reset (ATR) counters: • ...
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... NXP Semiconductors When operating, the microcontroller starts to configure the selected card slot (card supply voltage) and then triggers the activation sequence using the START bit. The sequencer then performs the activation sequence. The DC-to-DC converter is started, pin V set to the previously configured card supply voltage, pin I/O (see Section 8 ...
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... NXP Semiconductors The sequence described in answered), the microcontroller can start a warm reset by setting WARM bit to logic 1 (see the bit descriptions in counter set pin RST Remark assumed that two card activations will not take place simultaneously on card slots because only one I/O protection on the second ATR counter against starting an activation while a count is ongoing. The fi ...
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... NXP Semiconductors The fall time is calculated from the signal amplitude. The default setting for IO_SR[0]/IO_SR[2] (low) and IO_SR[1]/IO_SR[3] (high) is LOW (see table page 37). 8.11 Fault detection The following fault conditions are monitored by the TDA8026. • Overheating: All the card slots are automatically deactivated and the device is forced in to Standby mode when the detected temperature range is between 125 C to 209 C ...
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... NXP Semiconductors 9. Limiting values Table 40. In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol DD(INTF tot T stg V ESD [1] The limiting values depend on the external inductor and V [2] Every pin withstands the ESD test according to MIL-STD-883C class 3 for card contacts, class 2 for the remaining. Method 3015 (HBM ...
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... NXP Semiconductors 11. Characteristics Table 42 pins V DD Symbol hys V DD(INTF DD(INTF) t wake [1] f clk(ext) [2] Refer to [3] See [4] See [5] Typical value measurement based DC-to-DC converter and inductance efficiency; depends on PCB layout and external component quality (inductor, capacitor). [6] Maximum measurement value based on a 125 mA I inductance effi ...
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... NXP Semiconductors Table 44. DC-to-DC converter 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V and V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter f internal oscillator osc(int) frequency V output voltage o V input voltage i t DC-to-DC converter on(DCDC) turn-on time Table 45. ...
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... NXP Semiconductors Table 45. Card drivers …continued 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter I supply current CC SR slew rate C decoupling capacitance dec Card reset output pins: RST (1) V output voltage o I output current ...
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... NXP Semiconductors Table 45. Card drivers …continued 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter clock duty cycle clk SR slew rate Data line pins: I (1) (5) V output voltage o I output current ...
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... NXP Semiconductors Table 45. Card drivers …continued 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter Card presence input: pin PRES; active HIGH when SPRES pin = LOW or active LOW when SPRES pin = HIGH ...
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... NXP Semiconductors Table 47. Interface signals to microcontroller 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter t output rise time r(o) t input rise time r(i) t output fall time f(o) t input fall time f(i) C input capacitance ...
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... NXP Semiconductors Table 47. Interface signals to microcontroller 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter Logic input pin: INTAUXN V LOW-level input IL voltage V HIGH-level input IH voltage I LOW-level input LIL leakage current C input capacitance ...
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... NXP Semiconductors Table 47. Interface signals to microcontroller 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pins V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter Serial data input/output pin: SDA; open-drain V LOW-level input IL voltage V HIGH-level input IH voltage V LOW-level output OL voltage I HIGH-level leakage ...
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... NXP Semiconductors Table 48. Protections 3 MHz; GND = 0 V; inductor = 10 H; decoupling capacitors on pin V DD DD(INTF) clk(ext unless otherwise specified. amb Symbol Parameter T shutdown temperature sd shutdown current output current limit Olim T ambient temperature amb T junction temperature j supply current I CC SDA LOW f r SCL t HD ...
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V DD(INTF) PORADJ DCDC_OFF C11 SDWNN V 100 nF DD(INTF 3.3 k SCL MICROCONTROLLER R pu 3.3 k SDA R1 100 k IRQN A0 INTAUX I/OUC1 I/OUC2 CLKIN1 CLKIN2 SPRES GND2 to GND10 TESTMODE INHIB TST1 TST2 (1) ...
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... NXP Semiconductors 13. Package outline TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) UNIT max 1.2 0.35 0.85 mm nom 1.1 0.30 0.80 min 1.0 0.25 0.75 OUTLINE VERSION IEC SOT1073 Fig 15 ...
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... NXP Semiconductors 14. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 14.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits ...
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... NXP Semiconductors 14.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board • ...
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... NXP Semiconductors Fig 16. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 15. Abbreviations Table 51. Acronym ATR CDM ESD ESR HBM LSB MM MSB PCB POR POS SAM 16 ...
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... NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. ...
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... In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors’ warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 19. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3 Table 3. TDA8026 ball map . . . . . . . . . . . . . . . . . . . . . . .5 Table 4. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6 Table 5. Base addressing . . . . . . . . . . . . . . . . . . . . . . .14 Table 6. Write mode addresses . . . . . . . . . . . . . . . . . .14 Table 7. Register overview . . . . . . . . . . . . . . . . . . . . . .16 Table 8. Bank 0 register (address: 48h) bit allocation . .18 Table 9. Bank 0 bit description . . . . . . . . . . . . . . . . . . .18 Table 10. Bank 1 CSb[7:0] Register0 (address 40h) card slot 1 and card slot 2 bit allocation ...
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... NXP Semiconductors 20. Figures Fig 1. TDA8026 Block diagram . . . . . . . . . . . . . . . . . . . .4 Fig 2. TDA8026 pin configuration for the TFBGA64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 3. TDA8026 Power diagram . . . . . . . . . . . . . . . . . . . .8 Fig 4. The enter shutdown sequence .10 Fig 5. The exit shutdown sequence . . . . . . . . . . . . . . . .10 Fig 6. The voltage supervisor circuit . . . . . . . . . . . . . . .11 Fig 7. V voltage supervisor . . . . . . . . . . . . . . . . . . . .11 DD Fig 8. ...
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... NXP Semiconductors 21. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefi Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 Power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2.1 Standby mode ...
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... NXP Semiconductors 8.5.4.9 Bank 1 Register1 (REG[1:0] = 10) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) read/write mode bit descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 28 8.5.4.10 Bank 1 Register1 (REG[1:0] = 11) card slot 3 (address 03h), card slot 4 (address 04h) and card slot 5 (address 05h) bit allocation . . . . . . . . . . 28 8 ...