TDA8007BHL/C3,118 NXP Semiconductors, TDA8007BHL/C3,118 Datasheet - Page 18

• Manufacturer Part Number: TDA8007BHL/C3,118
• Description: IC INTERFACE CARD MP 48-LQFP
• Manufacturer: NXP Semiconductors

Specifications of TDA8007BHL/C3,118

• Controller Type: Multiprotocol IC Card Interface
• Interface: Parallel
• Voltage - Supply: 2.7 V ~ 6 V
• Current - Supply: 315mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-3520-2; 935272525118; TDA8007BHLBE-T

NXP Semiconductors
TDA8007BHL
Product data sheet
8.2.2.3 Mixed Status Register (MSR)
The MSR relates the status of pin INTAUX, the cards presence contacts PRES1
and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive
ready indicator TBE/RBF. It also gives useful indications when switching the clock to or
from 1/2 f
No bits within register MSR act upon signal INT.
Table 15.
[1]
Table 16.
CLKSW
Bit
7
6
5
4
3
Register value at reset: bits TBE/RBF, BGT and CLKSW are cleared after reset; bits FE and CRED are set
after reset.
7
int
Symbol
CLKSW
FE
BGT
CRED
PR2
Register MSR (address 0Ch; read only)
Description of MSR bits
FE
and when driving the TDA8007BHL/C4 with fast controllers.
All information provided in this document is subject to legal disclaimers.
6
Rev. 8 — 11 January 2011
BGT
Description
clock switch: Bit CLKSW is set when the TDA8007BHL/C4 has
performed a required clock switch from
when the TDA8007BHL/C4 has performed a required clock switch from
1
before sending a new command to the card. This bit is reset at
power-on.
FIFO Empty: Bit FE is set when the reception FIFO is empty. It is reset
when at least one character has been loaded in the FIFO.
block guard time: In protocol T = 1, bit BGT is linked with a 22-ETU
counter which is started at every START bit on pin I/O. Bit BGT is set if
the count is finished before the next START bit. This helps to verify that
the card has not answered before 22 ETU after the last transmitted
character, or that the reader is not transmitting a character before
22 ETU after the last received character.
In protocol T = 0, bit BGT is linked with a 16-ETU counter which is
started at every START bit on pin I/O. Bit BGT is set if the count is
finished before the next START bit. This helps to verify that the reader
is not transmitting a character before 16 ETU after the last received
character.
control ready: It is advised bit CRED is used for driving the
TDA8007BHL/C4 with high speed controllers. Before writing in
registers TOC or UTR, or reading from register URR, check if bit CRED
is set. If reset, it means that the writing or reading operation will not be
correct because the controller is acting faster than the required time for
this operation:
card 2 present: Bit PR2 = 1 when card 2 is present.
⁄
2
f
5
int
to
1
⁄
n
CRED
f
XTAL
4
. The application must wait until this bit is set or reset
PR2
[1]
3
PR1
Multiprotocol IC card interface
1
2
TDA8007BHL
⁄
n
f
XTAL
to ⁄
INTAUX
2
f
© NXP B.V. 2011. All rights reserved.
int
1
, and is reset
TBE/RBF
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0