AD1980JSTZ Analog Devices Inc, AD1980JSTZ Datasheet - Page 26

• Manufacturer Part Number: AD1980JSTZ
• Description: IC CODEC STEREO 6-DAC 20B 48LQFP
• Manufacturer: Analog Devices Inc
• Series: SoundMAX®r
• Type: Audio Codec '97r

Specifications of AD1980JSTZ

• Data Interface: Serial
• Resolution (bits): 16, 20 b
• Number Of Adcs / Dacs: 2 / 6
• Sigma Delta: No
• Dynamic Range, Adcs / Dacs (db) Typ: 82 / 90
• Voltage - Supply, Analog: 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.15/4.75V
• Single Supply Voltage (max): 3.45/5.25V
• Package Type: LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD1980
All registers not shown and bits containing an X are assumed to be reserved.
Note that this register is not reset when the reset register (0x00) is written to (soft reset).
SPLNK
SPDZ
SPAL
INTS
LBKS[1:0]
CHEN
DRF
REGM3
REGM0
REGM1
REGM2
SLOT16
Reg
No. Name D15
74h Serial
Configuration
SLOT16 REGM2 REGM1 REGM0 REGM3 DRF X
SPDIF Link. This bit enables the SPDIF to link with the front DACs for data requesting.
0 = SPDIF and DAC are not linked.
1 = SPDIF and DAC are linked and receive the same data requests (reset default).
SPDIF DACZ.
0 = Repeat last sample out of the SPDIF stream if FIFO under-runs (reset default).
1 = Forces midscale sample out the SPDIF stream if FIFO under-runs.
SPDIF ADC Loop-around.
0 = SPDIF transmitter is connected to the AC-Link stream (reset default).
1= SPDIF transmitter is connected to the digital ADC stream, not the AC-Link.
Interrupt Mode Select. This bit selects the JS interrupt implementation path.
0 = Bit 0 SLOT 12 (modem interrupt) (reset default).
1 = Slot 6 Valid Bit (MIC ADC interrupt).
Loop-Back Selection. These bits select the internal digital loop-back path when LPBK bit is active (see Register 20h)
00 = Loop back through the front DACs (reset default).
01 = Loop back through the surround DACs.
10 = Reserved
11 = Loop-back through the center and LFE DACs (Center DAC loops back from the ADC left channel, the LFE
DAC from the ADC right channel).
Chain Enable. This bit enables chaining of a slave codec SDATA_IN stream into the ID0 pin (Pin 45).
0 = Disable chaining (reset default).
1 = Enable chaining into ID0 pin.
DAC Request Force. This allows the AD1980 to synchronize DAC requests with the AD1981A/B.
0 = Normal DAC requesting sequence (reset default).
1 = Synchronize to AD1981A/B DAC requests.
Slave 3 Codec Register Mask
Master Codec Register Mask
Slave 1 Codec Register Mask
Slave 2 Codec Register Mask
Enable 16-Bit Slot Mode. SLOT16 makes all ac-link slots 16 bits in length, formatted into 16 slots. This is a
preferred mode for DSP serial port interfacing.
D14
D13
D12
Serial Configuration Register (Index 74h)
D11
D10 D9 D8
–26–
CHEN X
D7 D6
LBKS1 LBKS0 INTS X
D5
D4
D3 D2
SPAL SPDZ SPLNK 1001h
D1
D0
Default
REV. 0