AD1980JSTZ Analog Devices Inc, AD1980JSTZ Datasheet

IC CODEC STEREO 6-DAC 20B 48LQFP

AD1980JSTZ

Manufacturer Part Number
AD1980JSTZ
Description
IC CODEC STEREO 6-DAC 20B 48LQFP
Manufacturer
Analog Devices Inc
Series
SoundMAX®r
Type
Audio Codec '97r
Datasheet

Specifications of AD1980JSTZ

Data Interface
Serial
Resolution (bits)
16, 20 b
Number Of Adcs / Dacs
2 / 6
Sigma Delta
No
Dynamic Range, Adcs / Dacs (db) Typ
82 / 90
Voltage - Supply, Analog
4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Single Supply Voltage (typ)
3.3/5V
Single Supply Voltage (min)
3.15/4.75V
Single Supply Voltage (max)
3.45/5.25V
Package Type
LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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AD1980JSTZ
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Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
SURR_OUT_R/
SURR_OUT_L/
CENTER_OUT
LINE_OUT_R
LINE_OUT_L
MONO_OUT
HP_OUT_R
HP_OUT_L
PHONE_IN
LINE_IN_R
LINE_IN_L
FEATURES
AC ’97 2.3 COMPATIBLE FEATURES
6 DAC Channels for 5.1 Surround
S/PDIF Output
Integrated Stereo Headphone Amplifier
Variable Rate Audio
Double Rate Audio (f
Greater than 90 dB Dynamic Range
20-Bit PCM DACs
Line-Level Mono ”Phone” Input
High Quality CD Input
Selectable MIC Input with Preamp
AUX and Line_In Stereo Inputs
External Amplifier Power-Down Control
Power Management Modes
48-Lead LQFP Package
LFE_OUT
CD_GND
AUX_R
AUX_L
CD_R
CD_L
MC1
MC2
HP
HP
MZ
MZ
MZ
DIFF AMP
MZ
MZ
CD
M
M
AD1980
A
A
A
A
A
A
A
S
= 96 kHz)
MIC PREAMP
G
G
M
M
GA
M
GA
M
M
GA
M
GA
M
FUNCTIONAL BLOCK DIAGRAM
V
GA
REFOUT
M
GA
M
GA
M
M
G
GA
M
V
REF
M
M
REFERENCE
ENHANCED FEATURES
Integrated Parametric Equalizer
Stereo MIC Preamp Support
Integrated PLL for System Clocking
Variable Sample Rate 7 kHz to 96 kHz
Jack Sense (Auto Topology Switching)
Software Controlled VREF_OUT for MIC Bias
Software Enabled Outputs for Jack Sharing
Auto Down-Mix and Channel Spreading Modes
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
VOLTAGE
G = GAIN
A = ATTENUATION
M = MUTE
Z = HIGH Z
M
M
M
M
G
G
M
M
G
G
G
G
M
G
G
M
AC ’97 SoundMAX
PCM FRONT
PCM SURR
ADC RATE
DAC RATE
DAC RATE
DAC RATE
16-BIT
16-BIT
PCM LFE
20-BIT
20-BIT
20-BIT
20-BIT
20-BIT
20-BIT
- ADC
- ADC
PCM L/R
- DAC
- DAC
- DAC
- DAC
- DAC
- DAC
CODEC CORE
© 2002 Analog Devices, Inc. All rights reserved.
EQ
EQ
XTL_OUT XTL_IN SPDIF
PLL
CONTROL LOGIC
ANALOG MIXING
LOGIC
SLOT
DAC
JS0
REGISTERS
AD1980
CONTROL
JS1
AC '97
SPDIF
www.analog.com
TX
®
EAPD
EAPD
Codec
ID0
ID1
RESET
SYNC
BITCLK
SDATA_OUT
SDATA_IN

Related parts for AD1980JSTZ

AD1980JSTZ Summary of contents

Page 1

FEATURES AC ’97 2.3 COMPATIBLE FEATURES 6 DAC Channels for 5.1 Surround S/PDIF Output Integrated Stereo Headphone Amplifier Variable Rate Audio Double Rate Audio ( kHz) S Greater than 90 dB Dynamic Range 20-Bit PCM DACs Line-Level ...

Page 2

AD1980–SPECIFICATIONS STANDARD TEST CONDITIONS, UNLESS OTHERWISE NOTED Temperature 25°C Digital Supply ( Analog Supply ( Sample Rate ( kHz S Input Signal 1008 Hz Analog Output Pass Band 20 Hz ...

Page 3

Parameter ANALOG-TO-DIGITAL CONVERTERS Resolution Total Harmonic Distortion (THD) AV Dynamic Range (–60 dB Input THD + N Referenced to FS, A-Weighted 5 Signal-to-Intermodulation Distortion * ADC Crosstalk Line Inputs (Input L, Ground R, Read R; Input ...

Page 4

AD1980 Parameter PR[K:I] 2 POWER-DOWN STATES Fully Active 000 ADC 000 FRONT DAC 000 SURROUND DAC 010 CENTER/LFE DAC 101 ADC + ALL DACs 111 Mixer 000 ADC + Mixer 000 ALL DACs + Mixer 111 ADC + ALL DACs ...

Page 5

RESET BIT_CLK SDATA_IN Figure 1. Cold Reset Timing (Codec is Supplying the Bit_CLK Signal) SYNC BIT_CLK t CLK_LOW BIT_CLK t CLK_HIGH t CLK_PERIOD t SYNC_LOW SYNC t SYNC_HIGH t SYNC_PERIOD Figure 3. Clock Timing BIT_CLK t RISECLK SYNC t RISESYNC ...

Page 6

AD1980 ABSOLUTE MAXIMUM RATINGS* Parameter Min Power Supplies Digital (DV ) –0.3 DD Analog (AV ) –0.3 DD Input Current (Except Supply Pins) Analog Input Voltage (Signal Pins) –0.3 Digital Input Voltage (Signal Pins) –0.3 Ambient Temperature (Operating) 0 Storage ...

Page 7

Pin Number Mnemonic DIGITAL INPUT/OUTPUT 2 XTL_IN 3 XTL_OUT 5 SDATA_OUT 6 BIT_ CLK 8 SDATA_IN 10 SYNC RESET 11 48 SPDIF CHIP SELECTS/CLOCK STRAPPING ID0 45 ID1 46 JACK SENSE AND EAPD 47 EAPD 17 JS0 16 JS1 ANALOG ...

Page 8

AD1980 Pin Number Mnemonic POWER AND GROUND SIGNALS ...

Page 9

Reg Name D15 D14 D13 00h Reset X SE4 SE3 02h Master Volume MM X LMV5 04h Headphone HPM X LHV5 Volume 06h Mono Volume MVM X X 0Ch Phone Volume PHM X X 0Eh Mic Volume MCM X X ...

Page 10

AD1980 Reg No. Name D15 D14 D13 D12 00h Reset X SE4 SE3 SE2 NOTES All registers not shown and bits containing an X are assumed to be reserved. Writing any value to this register performs a register reset, which ...

Page 11

Reg No. Name D15 D14 D13 04h Headphones HPM X LHV5 LHV4 LHV3 LHV2 LHV1 LHV0 HPRM* X Volume *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables separate ...

Page 12

AD1980 Reg No. Name D15 D14 D13 0Ch Phone_in Volume PHM X X All registers not shown and bits containing an X are assumed to be reserved. Refer to Table III for examples. PHV[4:0] Phone Volume. Allows setting the Phone ...

Page 13

Reg No. Name D15 D14 D13 D12 10h Line-In Volume LVM X X LLV4 LLV3 LLV2 LLV1 LLV0 LVRM* X *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT bit enables ...

Page 14

AD1980 Reg No. Name D15 D14 D13 D12 18h PCM Out Volume LOV4 LOV3 LOV2 LOV1 LOV0 OMRM* X *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. The MSPLT ...

Page 15

LS [10:8] 000 001 010 011 100 101 110 111 Reg No. Name D15 D14 D13 D12 1Ch Record Gain *For AC ’97 compatibility, Bit D7 is available only by setting the MSPLT bit, Register 76h. ...

Page 16

AD1980 Reg No. Name D15 D14 D13 20h General-Purpose This register should be read before writing to generate a mask for only the bit(s) that need to be changed. All registers not shown and bits containing an ...

Page 17

Reg No. Name D15 D14 26h Power-Down EAPD PR6 Control/Status The ready bits are read only; writing to REF, ANL, DAC, ADC will have no effect. These bits indicate the status for the AD1980 subsections. If the bit is a ...

Page 18

AD1980 PR0 = 1 NORMAL PR0 = 0 AND ADC = 1 READY = 1 Figure 8. One Example of AC ‘97 Power-Down/Power-Up Flow Reg No. Name D15 D14 D13 D12 D11 28h Ext’d Audio ID1 ID0 X X The ...

Page 19

Extended Audio Status and Control Register (Index 2Ah) Reg No. Name D15 D14 D13 D12 D11 D10 2Ah Extended Audio VFORCE X PRK PRJ PRI SPCV X Stat/Ctrl The extended audio status and control register is a read/write register that ...

Page 20

AD1980 AC ’97 2.2 AMAP Compliant Default SPDIF Slot Assignments Codec ID Function 00 2-Ch Primary w/SPDIF 00 4-Ch Primary w/SPDIF 00 6-Ch Primary w/SPDIF 01 +2-Ch Secondary w/SPDIF 01 +4-Ch Secondary w/SPDIF 10 +2-Ch Secondary w/SPDIF 10 +4-Ch Secondary ...

Page 21

Reg No. Name D15 D14 D13* D12 36h Center/LFE LM X LFE5 LFE4 Volume All registers not shown and bits containing an X are assumed to be reserved. Refer to Table VII for examples. This register controls the LFE output ...

Page 22

AD1980 Left Surround D[13:8] Right Surround D[5:0] D15/D7 WRITE READBACK 0 00 0000 00 0000 0 00 1111 00 1111 0 01 1111 01 1111 0 1x xxxx 01 1111 1 xx xxxx xx xxxx Reg No. Name D15 D14 ...

Page 23

Reg No. Name D15 D14 D13 60h EQ CTRL EQM X X All registers not shown, and bits containing an X are assumed to be reserved. Register 60h is a read/write register that controls the Equalizer functionality and data setup. ...

Page 24

AD1980 Reg No. Name D15 D14 D13 D12 62h EQ DATA CFD15 CFD14 CFD13 CFD12 CFD11 CFD10 CFD9 CFD8 CFD7 CFD6 CFD5 CFD4 CFD3 CFD2 CFD1 CFD0 0000h This read/write register is used to transfer EQ biquad coefficients into memory. ...

Page 25

REF JS1 JS0 JSMT2 JSMT1 JSMT0 OUT 0 OUT (0) OUT ( OUT ( (1) OUT ( ( OUT (0) OUT ( OUT (0) ...

Page 26

AD1980 Reg No. Name D15 D14 D13 74h Serial SLOT16 REGM2 REGM1 REGM0 REGM3 DRF X Configuration All registers not shown and bits containing an X are assumed to be reserved. Note that this register is not reset when the ...

Page 27

Reg No. Name D15 D14 D13 D12 76th Misc DACZ AC97NC MSPLT LODIS CLDIS HPSEL DMIX1 DMIX0 SPRD 2CMIC LOSEL SRU VREFH VREFD MBG1MBG0 0000h Control Bits MBG[1:0] MIC Boost Gain Select Register. These two bits allow changing the MIC ...

Page 28

AD1980 DMIX[1:0] Down Mix Mode Select. Provides analog down-mixing of the center, LFE, and/or surround channels into the mixer channels. This allows the full content of 5.1 or quad media to be played through stereo headphones or speakers. Note that ...

Page 29

Reg No. Name D15 D14 D13 7Ch Vendor ID1 S[7:0] This register is ASCII encoded to A. F[7:0] This register is ASCII encoded to D. Reg No. Name D15 D14 D13 D12 D11 D10 ...

Page 30

AD1980 1.45 1.40 1.35 0.15 SEATING 0.05 PLANE ROTATED 90 CCW OUTLINE DIMENSIONS 48-Lead Plastic Quad Flatpack [LQFP] 1.4 mm Thick (ST-48) Dimensions shown in millimeters 1.60 MAX PIN 1 INDICATOR 0.75 0.60 0.45 SEATING PLANE 0.20 0.09 VIEW A ...

Page 31

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