IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 33

• Manufacturer Part Number: IDTSTAC9753AXNAED1XR
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1XR

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1XR

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
5.2.1.
5.2.2.
AC-Link Variable Sample Rate Operation
The AC-Link serial interconnect defines a digital data and control pipe between the Controller and
the CODEC. The AC-Link supports twelve 20-bit slots at 48KHz on SDATA_IN and SDATA_OUT.
The time division multiplexed (TDM) “slot-based” architecture supports a per-slot valid tag infrastruc-
ture that the source of each slot’s data sets or clears to indicate the validity of the slot data within the
current audio frame. This tag infrastructure can be used to support transfers between Controller and
CODEC at any sample rate.
Variable Sample Rate Signaling Protocol
AC-Link’s tag infrastructure imposes FIFO requirements on both sides of the AC-Link. For example,
in passing a 44.1KHz stream across the AC-Link, for every 480 audio output frames that are sent
across, 441 of them must contain valid sample data. Does the AC‘97 Digital Controller pass all 441
PCM samples followed by 39 invalid slots? Or does the AC‘97 Digital Controller evenly interleave
valid and non-valid slots? Each possible method brings with it different FIFO requirements. To
achieve interoperability between AC‘97 Digital Controllers and CODECs designed by different man-
ufacturers, it is necessary to standardize the scheme for at least one side of the AC-Link so that the
FIFO requirements will be common to all designs. The CODEC side of the AC-Link is the focus of
this standardization.
The new standard approach calls for the addition of “on demand” slot request flags. These flags are
passed from the CODEC to the AC‘97 Digital Controller during every audio input frame. Each time
the AC‘97 Digital Controller sees one or more of the newly-defined slot request flags set active (low)
in a given audio input frame, it knows that it must pass along the next PCM sample for the corre-
sponding slot(s) in the AC-Link output frame that immediately follows.
The VRA (Variable Rate Audio) bit in the Extended Audio Status and Control Register must be set to
1 to enable variable sample rate audio operation. Setting the VRA = 1 has two functions:
1. Enables PCM DAC/ADC conversions at variable sample rates by write enabling Sample Rate
2. Enables the on demand CODEC-to-Controller signaling protocol using SLOTREQ bits that
The table below summarizes the behavior:
For variable sample rate output, the CODEC examines its sample rate control registers, the state of
its FIFOs, and the incoming SDATA_OUT tag bits at the beginning of each AC-Link output frame to
determine which SLOTREQ bits to set active (low). SLOTREQ bits asserted during the current
Note: If more than one CODEC is being used with the SAME controller DMA engine, VRA should NOT be
Registers 2C-34h.
becomes necessary when a DAC’s sample rate varies from the 48KHz AC-Link serial frame
rate.
AC‘97 Functionality
sample rate registers
used.
SLOTREQ bits
always 0 (data each frame)
33
Table 6. VRA Behavior
forced to 48KHz
VRA = 0
STAC9752A/9753A
0 or 1 (data on demand)
VRA = 1
writable
PC AUDIO
V 1.5 1206