IDTSTAC9753AXNAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1XR Datasheet - Page 26

IC CODEC AC'97 MIC/JACK 32-QFN

IDTSTAC9753AXNAED1XR

Manufacturer Part Number
IDTSTAC9753AXNAED1XR
Description
IC CODEC AC'97 MIC/JACK 32-QFN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec '97r
Datasheet

Specifications of IDTSTAC9753AXNAED1XR

Resolution (bits)
20 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
85 / 92
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-QFN
Single Supply Voltage (typ)
3.3/5V
Single Supply Voltage (min)
3.135V
Single Supply Voltage (max)
3.465/5.25V
Package Type
VFQFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
STAC9753AXNAED1XR
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
4.3.
Controller to Multiple CODECs
If, when the RESET# signal has been de-asserted, the CODEC has not detected a signal on
BIT_CLK as defined in the previous paragraph then the AC‘97 CODEC derives its clock internally
from an externally attached 24.576MHz crystal or oscillator, or optionally from an external
14.318MHz oscillator, and drives a buffered 12.288MHz clock to its digital Controller over AC-Link
under the signal name “BIT_CLK”. Clock jitter at the DACs and ADCs is a fundamental impediment
to high quality output, and the internally generated clock will provide AC‘97 components with a clean
clock that is independent of the physical proximity of AC‘97’s Digital Controller (henceforth referred
to as “the Controller”).
If BIT_CLK begins toggling while the RESET# signal is still asserted, the clock is being provided by
other than the primary CODEC, for instance by the controller or by a discrete clock source. In this
case, the primary CODEC must act as a consumer of the BIT_CLK signal as if it were a secondary
CODEC.
The beginning of all audio sample packets, or Audio Frames, transferred over AC-Link is synchro-
nized to the rising edge of the SYNC signal. SYNC is driven by the Controller. The Controller gener-
ates SYNC by dividing BIT_CLK by 256 and applying some conditioning to tailor its duty cycle. This
yields a 48 KHz SYNC signal whose period defines an audio frame. Data is transitioned on AC-Link
on every rising edge of BIT_CLK, and subsequently sampled by the receiving device on the receiv-
ing side of AC-Link on each immediately following falling edge of BIT_CLK.
Several vendor specific methods of supporting multiple CODEC configurations on AC-Link have
been implemented or proposed, including CODECs with selective AC-Link pass-through and con-
trollers with duplicate AC-Links.
Potential implementations include:
This specification defines support for up to four CODECs on the AC-Link. By definition there can be
one Primary CODEC (ID 00) and up to three Secondary CODECs (IDs 01,10, and 11). The CODEC
ID functions as a chip select. Secondary devices therefore have completely orthogonal register sets;
each is individually accessible and they do not share registers.
Multiple CODEC AC-Link implementations must run off a common BIT_CLK. They can potentially
save Controller pins by sharing SYNC, SDATA_OUT, and RESET# from the AC‘97 Digital Control-
ler. Each device requires its own SDATA_IN pin back to the Controller. This prevents contention of
multiple devices on one serial input line.
Support for multiple CODEC operation necessitates a specially designed Controller. An AC‘97 Digi-
tal Controller that supports multiple CODEC configurations implements multiple SDATA_IN inputs,
supporting one Primary CODEC and up to three Secondary CODECs.
6-channel audio using 3 x 2-channel CODECs
Separate CODECs for independent audio and modem AFE
Docking stations, where one CODEC is in the laptop and another is in the dock
26
STAC9752A/9753A
PC AUDIO
V 1.5 1206

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