IP-NIOS Altera, IP-NIOS Datasheet - Page 82

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

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Nios II Processor Reference Handbook
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External Interrupt Controller Interface
The Nios II EIC interface enables you to connect the Nios II processor to an external
interrupt controller component. The EIC can monitor and prioritize IRQ signals, and
determine which interrupt to present to the Nios II processor. An EIC can be
software-configurable.
The Nios II processor does not depend on any particular implementation of an EIC.
The degree of EIC configurability, and EIC configuration methods, are
implementation-specific. This section discusses the EIC interface, and general features
of EICs. For usage details, refer to the documentation for the specific EIC in your
system.
For a typical EIC implementation, refer to the Vectored Interrupt Controller chapter in
the
When an IRQ is asserted, the EIC presents the following information to the Nios II
processor:
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The Nios II processor EIC interface connects to a single EIC, but an EIC can support a
daisy-chained configuration. In a daisy-chained configuration, multiple EICs can
monitor and prioritize interrupts. The EIC directly connected to the processor
presents the processor with the highest-priority interrupt from all EICs in the daisy
chain.
An EIC component can support an arbitrary level of daisy-chaining, potentially
allowing the Nios II processor to handle an arbitrary number of prioritized interrupts.
Requested Handler Address
The RHA specifies the address of the handler associated with the interrupt. The
availability of an RHA for each interrupt allows the Nios II processor to jump directly
to the interrupt handler, reducing interrupt latency.
The RHA for each interrupt is typically software-configurable. The method for
specifying the RHA is dependent on the specific EIC implementation.
If the Nios II processor is implemented with an MMU, the processor treats handler
addresses as virtual addresses.
Requested Interrupt Level
The Nios II processor uses the RIL to decide when to take a maskable interrupt. The
interrupt is taken only when the RIL is greater than status.IL.
The RIL is ignored for nonmaskable interrupts.
The external interrupt controller interface
The internal interrupt controller
The requested handler address (RHA)—Refer to
The requested interrupt level (RIL)—Refer to
The requested register set (RRS)—Refer to
Requested nonmaskable interrupt (RNMI) mode—Refer to
Mode”
Embedded Peripherals IP User
Guide.
“Requested Register Set”
“Requested Interrupt Level”
“Requested Handler Address”
December 2010 Altera Corporation
Chapter 3: Programming Model
“Requested NMI
Exception Processing