IP-NIOS Altera, IP-NIOS Datasheet - Page 120

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

4–12
MMU and MPU Settings Page
Figure 4–4. MMU and MPU Settings Page in the Nios II Processor Parameter Editor
Nios II Processor Reference Handbook
Shadow Register Sets
f
1
The Number of shadow register sets setting determines whether the Nios II core
implements shadow register sets. The Nios II core can be configured with up to 63
shadow register sets.
Shadow register sets are available only on the Nios II/f core.
When the EIC interface and shadow register sets are implemented on the Nios II core,
you must ensure that your software is built with the Nios II EDS version 9.0 or higher.
For details about shadow register sets, refer to “Registers” in the
chapter of the Nios II Processor Reference Handbook.
The MMU and MPU Settings page presents settings for configuring the MMU and
MPU on the Nios II processor. You can select the features appropriate for your target
application.
Figure 4–4
shows the MMU and MPU Settings page.
Chapter 4: Instantiating the Nios II Processor in SOPC Builder
December 2010 Altera Corporation
MMU and MPU Settings Page
Programming Model