MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 389

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MC68060 Software Package
ifying the call-out dispatch table, keep in mind that these need to be supplied and filled-in
with module-relative, and not absolute addresses.
The next step is to prepare the exception vector table. The appropriate vector table entries
must be filled with the addresses of the appropriate entry points. Since the modified pseudo-
assembly module contains symbols that indicate the top of the module, the appropriate vec-
tor table entries must contain the symbol of the appropriate module top plus the pre-defined
offset. Another alternative is to use the module code size information given in Table C-1 to
concatenate the modules and use a single symbolic label to describe the combined module.
Figure C-12 illustrates the relationship of the vector table to the M68060SP.
The last step is to link everything. Be aware that the files must be linked such that the parts
of the module that are in different files are kept together. Be aware that the included files
are for a very simple installation procedure and may not be appropriate for all systems. For
instance, the supplied _real_trace routine would be inappropriate for a system in which the
trace vector table entry is dynamically changed. For that system, the _real_trace routine
must include vector table query before jumping to the actual trace routine.
C.5.3 Release Notes and Module Offset Assignments
To obtain the most up-to-date offset assignments for the call-out dispatch table and the mod-
ule Entry-point Dispatch Section assignments, four document files are provided with the
M68060SP release. The files isp.doc, ilsp.doc, fpsp.doc, and fplsp.doc define the offsets for
the unimplemented integer instruction exception handler, unimplemented integer subrou-
tine, full (or partial) floating-point kernel and floating-point library modules respectively. The
current module sizes are shown in Table C-1. If a module increases in code size or if addi-
tional entry points are made available in future releases, they will be documented in these
four files.
C-28
NOTE: X_060SP represents a generic M68060SP handler entry point and is not intended to imply a single shared handler entry
point for all MC68060 exception handlers.
VECTOR TABLE
VECTOR ENTRY
(A) STRAIGHT ENTRY
Figure C-12. Vector Table and M68060SP Relationship
jmp os_done
x_060SP:
M68060 USER’S MANUAL
OR
OS_done:
os_code:
jmp
<os finish>
rte
<os start>
x_060SP
(B) INDIRECT ENTRY
VECTOR ENTRY
VECTOR TABLE
MOTOROLA