MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 108

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Caches
and an exception occurs, the instruction is aborted, and the operand may be accessed again
when the instruction is restarted. These guarantees apply only when the CM field indicates
the precise mode and the accesses are aligned. Regardless of the selected cache mode,
locked accesses are implicitly precise. Locked accesses are performed by the MC68060 for
the operands of the TAS and CAS instructions, and for updating history information in the
translation tables during table search operations.
5.4.3 Special Accesses
Several other processor operations result in accesses that have special caching character-
istics besides those with an implied cache-inhibited access in the precise mode. Exception
stack accesses and exception vector fetches that miss in the cache do not allocate cache
lines in the data cache, preventing replacement of a cache line. Cache hits by these
accesses are handled in the normal manner according to the caching mode specified for the
accessed address.
MC68060-initiated MMU table searches bypass the cache.
Accesses by the MOVE16 instruction also do not allocate cache lines in the data cache for
either read or write misses. Read hits on either valid or dirty cache lines are read from the
cache. Write hits invalidate a matching line and perform an external access. Interacting with
the cache in this manner prevents a large block move or block initialization implemented with
a MOVE16 from being cached, since the data may not be needed immediately.
5.5 CACHE PROTOCOL
The cache protocol for processor and snooped accesses is described in the following para-
graphs. In all cases, an external bus transfer will cause a cache line state to change only if
the bus transfer is marked as snoopable on the bus by asserting the SNOOP signal. The
protocols described in the following paragraphs assume that the data is cachable (i.e.,
writethrough and copyback).
5.5.1 Read Miss
A processor read that misses in the cache causes the cache controller to request a bus
transaction that reads the needed line from memory and supplies the required data to the
integer unit. The line is placed in the cache in the valid state, unless the no-allocate bit (NAD
for the data cache or NAI for the instruction cache) for the corresponding cache in the CACR
is set. Snooped external reads that miss in the cache have no affect on the cache.
5.5.2 Write Miss
The cache controller handles processor writes that miss in the cache differently for
writethrough and copyback pages. Write misses to copyback pages cause a line read from
the external bus to load the cache line (unless the corresponding no-allocate bit, NAD or
NAI, in the CACR is set). The new cache line is then updated with the write data, and the D-
bit for the line is set, leaving the cache line in the dirty state. Write misses to writethrough
pages write directly to memory without loading the corresponding cache line in the cache.
Snooped external writes that miss in the cache have no affect on the cache.
MOTOROLA
M68060 USER’S MANUAL
5-9