MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 382

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

For example, the FSIN operation in Figure C-9(a) will take an unimplemented floating-point
instruction exception. If FSIN emulation discovers that the result should cause an underflow,
and underflow is disabled, then the fp0 register is assigned the default underflow result value
before program execution continues to the next integer or floating-point instruction.
C.3.2.4.2 Trap-Enabled Operation. If an exception is enabled and the instruction is of
opclass zero or two, then an FSAVE frame of that exception type is restored into the FPU
by the M68060FPSP. Second, the stack frame is cleaned up to the point just before the orig-
inal exception handler was entered. Next, the original exception stack frame is converted to
a stack frame for the new exception type. Finally, the handler returns the processor to nor-
mal processing. The new exception is then taken as a pre-instruction exception upon
encountering the next floating-point instruction.
From the previous FSIN example of Figure C-9(a), if the emulation encountered an under-
flow condition and underflow was enabled, an FSAVE frame with the underflow exception
bit set would be inserted into the FPU. An underflow pre-instruction exception would then be
taken upon encountering the next floating-point instruction.
This restoring procedure is used for enabled exceptions so that an exception will not enter
through an unimplemented data type, unimplemented effective address, or unimplemented
floating-point instruction exception and then exit through an SNAN, OPERR, OVFL, UNFL,
DZ, or INEX exception handler for an opclass zero or two instruction. Some operating sys-
tems may be confused by this type of flow change.
Opclass three instruction emulation that encounters an enabled exception is physically
unable to insert the appropriate exception frame into the FPU and return to normal process-
ing to await the next floating-point instruction. So, the M68060FPSP converts the existing
exception stack frame to a frame of the enabled exception’s type and inserts the exceptional
state into the FPU with an FRESTORE. Then, the M68060FPSP package branches to the
appropriate host operating system-supplied interface (_real_{SNAN, OPERR, OVFL, UNFL,
INEX}) for the enabled exception. This approach was also used with the MC68040FPSP.
C.3.3 Module 4: Partial Floating-Point Kernel
This module is identical to the full floating-point kernel in every aspect with the exception that
the floating-point unimplemented exception handler code is not included. This module is typ-
ically used with the floating-point library in a system that does not encounter MC68881
instructions that are unimplemented in the MC68060.
MOTOROLA
A “true” pre-instruction exception solution would have inserted
an FSAVE frame of type underflow into the FPU so that the un-
derflow processing would be delayed until the next floating-point
instruction triggered a pre-instruction underflow exception. The
approach taken by the M68060FPSP in this case avoids the
overhead of the second exception.
M68060 USER’S MANUAL
Note
MC68060 Software Package
C-21