MC68LC060RC66 Freescale Semiconductor, MC68LC060RC66 Datasheet - Page 148

• Manufacturer Part Number: MC68LC060RC66
• Description: IC MPU 32BIT 66MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68LC060RC66

• Processor Type: M680x0 32-Bit
• Speed: 66MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Floating-Point Unit
intermediate result format. When such an overflow occurs (called a catastrophic overflow),
the exception operand exponent value is set to $0000. This value is easily distinguished
from the exception operand exponent values produced by normal overflow processing.
If an INEX2 or INEX1 exceptional condition exists and the INEX exception is enabled, it is
the responsibility of the user OVFL handler to handle the lower priority inexact exception.
The user OVFL exception handler may discard the floating-point state frame once the han-
dler has completed. The RTE instruction must be executed to return to normal instruction
flow.
6.6.5 Underflow
An underflow exception occurs when the intermediate result of an arithmetic operation is too
small to be represented as a normalized number in a floating-point data register or memory
using the selected rounding precision. An arithmetic operation is too small when the inter-
mediate result exponent is less than or equal to the minimum exponent value of the selected
rounding precision. Underflow is not detected for intermediate result exponents that are
equal to the extended-precision minimum exponent since the explicit integer part bit permits
representation of normalized numbers with a minimum extended-precision exponent.
Underflow can only occur when the destination format is single, double, or extended preci-
sion. When the destination format is byte, word, or long word, the conversion underflows to
zero without causing either an underflow or an operand error. At the end of any operation
that could potentially underflow, the intermediate result is checked for underflow, rounded,
and checked for overflow before it is stored at the destination. If an underflow occurs, the
UNFL bit is set in the FPSR EXC byte.
Even if the intermediate result is large enough to be represented as an extended-precision
number, an underflow can occur. The intermediate result is rounded to the selected preci-
sion, and the rounded result is stored in extended-precision format. If the magnitude of the
intermediate result is too small to be represented in the selected rounding precision, an
underflow occurs.
The IEEE 754 standard defines two causes of an underflow: 1) when the absolute value of
the number is less than the minimum number that can be represented by a normalized num-
ber in a specific data format, or 2) when loss of accuracy occurs while attempting to calculate
such a number (a loss of accuracy also causes an inexact exception). The IEEE 754 stan-
dard specifies that if the underflow exception is disabled, an underflow should only be sig-
naled when both of these cases are satisfied (i.e., the result is too small to be represented
with a given format and there is a loss of accuracy during calculation of the final result). If
the exception is enabled, the underflow should be signaled any time a very small result is
produced, regardless of whether accuracy is lost in calculating it.
The processor UNFL bit in the FPSR AEXC byte implements the IEEE exception disabled
definition since it is only set when a very small number is generated and accuracy has been
lost when calculating that number. The UNFL bit in the FPSR EXC byte implements the
IEEE exception enabled definition since it is set any time a tiny number is generated.
The MC68060 is implemented such that when the UNFL bit of the FPCR is set, the proces-
sor always takes an exception regardless of whether or not the user UNFL exception han-
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M68060 USER’S MANUAL
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