MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 406

• Manufacturer Part Number: MC68040RC33V
• Description: IC MICROPROCESSOR 32BIT PGA-182
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC33V

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 182
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

C.6 MC68040V AND MC68EC040V JTAG (PRELIMINARY)
The MC68040V and MC68EC040V include dedicated user-accessible test logic that is
fully compatible with the IEEE standard 1149.1A Standard Test Access Port and
Boundary Scan Architecture . Problems associated with testing high-density circuit boards
have led to the standard’s development under the sponsorship of the IEEE Test
Technology Committee and the Joint Test Action Group (JTAG).
The following paragraphs are to be used in conjunction with the supporting IEEE
document and includes those chip-specific items that the IEEE standard requires to be
defined and additional information specific to the MC68040V and MC68EC040V
implementations. For example, the IEEE standard 1149.1A test access port (TAP)
controller states are referenced in this section but are not described. For these details and
application information regarding the standard, refer to the IEEE standard 1149.1A
document.
The MC68040V and MC68EC040V implementations support circuit board test strategies
based on the standard. The test logic utilizes static logic design and is system logic
independent of the device. The MC68040V and MC68EC040V implementations provide
capabilities to:
Figure C-4 illustrates a block diagram of the MC68040V and MC68EC040V
implementations of IEEE standard 1149.1A. The test logic includes a 16-state dedicated
TAP controller. These 16 controller states are defined in detail in the IEEE standard
1149.1A, but only 8 are included in this section.
Four dedicated signal pins provides access to the TAP controller:
C-10
a. Perform boundary scan operations to test circuit board electrical continuity,
b. Bypass the MC68040V and MC68EC040V by reducing the shift register path to a
c. Sample the MC68040V and MC68EC040V system pins during operation and
d. Disable the output drive to output-only pins during circuit board testing.
TCK—A test clock input that synchronizes the test logic.
TMS—A test mode select input with an internal pullup resistor sampled on the rising
single cell,
transparently shift out the result,
edge of TCK to sequence the TAP controller.
The IEEE standard 1149.1A test logic cannot be considered
completely benign to those planning not to use this capability.
Certain precautions must be observed to ensure that this logic
does not interfere with system operation. Refer to C.6.4
Disabling The IEEE Standard 1149.1A Operation.
Freescale Semiconductor, Inc.
Test-Logic-Reset
Capture-IR
Update-IR
Shift-IR
For More Information On This Product,
M68040 USER’S MANUAL
Go to: www.freescale.com
NOTE
Run-Test/Idle
Capture-DR
Update-DR
Shift-DR
MOTOROLA