MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 15

• Manufacturer Part Number: MC68040RC33V
• Description: IC MICROPROCESSOR 32BIT PGA-182
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC33V

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 182
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

1-1
1-2
2-1
2-2
2-3
2-4
2-5
3-1
3-2
3-3
3-4
3-5
3-6
3-7
3-8
3-9
3-10
3-11
3-12
3-13
3-14
3-15
3-16
3-17
3-18
3-19
3-20
3-21
3-22
3-23
4-1
4-2
4-3
4-4
MOTOROLA
Number
Figure
Block Diagram .............................................................................................. 1-4
Programming Model ..................................................................................... 1-7
Integer Unit Pipeline ..................................................................................... 2-2
Write-Back Cycle Block Diagram ................................................................. 2-3
Integer Unit User Programming Model......................................................... 2-4
Integer Unit Supervisor Programming Model ............................................... 2-6
Status Register............................................................................................. 2-7
Memory Management Unit ........................................................................... 3-2
Memory Management Programming Model ................................................. 3-3
URP and SRP Register Formats.................................................................. 3-4
Translation Control Register Format ............................................................ 3-4
Transparent Translation Register Format .................................................... 3-5
MMU Status Register Format....................................................................... 3-6
Translation Table Structure .......................................................................... 3-8
Logical Address Format ............................................................................... 3-9
Detailed Flowchart of Table Search Operation ............................................ 3-10
Detailed Flowchart of Descriptor Fetch Operation ....................................... 3-11
Table Descriptor Formats............................................................................. 3-13
Page Descriptor Formats ............................................................................. 3-13
Example Translation Table .......................................................................... 3-17
Translation Table Using Indirect Descriptors ............................................... 3-18
Translation Table Using Shared Tables ....................................................... 3-19
Translation Table with Nonresident Tables .................................................. 3-20
Translation Table Structure for Two Tasks .................................................. 3-24
Logical Address Map with Shared Supervisor and User Address Spaces... 3-24
Translation Table Using S-Bit and W-Bit To Set Protection ......................... 3-25
ATC Organization......................................................................................... 3-26
ATC Entry and Tag Fields ............................................................................ 3-27
Address Translation Flowchart..................................................................... 3-32
MMU Status Interpretation ........................................................................... 3-35
Overview of Internal Caches ........................................................................ 4-2
Cache Line Formats ..................................................................................... 4-3
Caching Operation ....................................................................................... 4-4
Cache Control Register ................................................................................ 4-5
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LIST OF ILLUSTRATIONS
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M68040 USER’S MANUAL
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Number
Page
xvii