MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 211

• Manufacturer Part Number: MC68040RC33V
• Description: IC MICROPROCESSOR 32BIT PGA-182
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC33V

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 182
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7.11.3 Data Latch Enable Mode
The data latch enable (DLE) mode allows read data to be latched by the assertion of the
DLE signal instead of by the BCLK rising edge at the end of each transfer. In some
applications, this mode can reduce the number of clocks required to perform line burst
reads. A logic zero on the MDIS enables this mode during a processor reset.
Figure 7-47 illustrates a conceptual block diagram of the logic used to latch the read data
bus in DLE mode. The DLE signal controls transparent latch A, which allows data to be
latched before the rising edge of BCLK. Latch A operates transparently when DLE is
negated and latches the level on the data bus when DLE is asserted. Note that the DLE
signal only controls latching of the read data and does not affect termination of the bus
MOTOROLA
Figure 7-46. Multiplexed Address and Data Bus (Line Write)
UPA1, UPA0
NOTE: The selected device increments the value of A3 and A2.
TLN1, TLN0
SIZ1, SIZ0
TM2–TM0
TT1, TT0
A31–A0
D31–D0
Freescale Semiconductor, Inc.
CIOUT
BCLK
R/W
For More Information On This Product,
TIP
TS
TA
A1, A0 =
Go to: www.freescale.com
C1
M68040 USER’S MANUAL
C2
01
C3
10
C4
11
C5
00
7- 69