MC68040RC33V Freescale Semiconductor, MC68040RC33V Datasheet - Page 365

• Manufacturer Part Number: MC68040RC33V
• Description: IC MICROPROCESSOR 32BIT PGA-182
• Manufacturer: Freescale Semiconductor

Specifications of MC68040RC33V

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 179-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 182
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

A.2 INTERRUPT PRIORITY LEVEL (IPL2 –I PL0)
The IPL2–IPL0 pins do not have any affect on the selection of output buffer impedance.
A.3 JTAG SCAN (JS0)
The MC68040 DLE pin name has been changed to JS0. During normal operation, the JS0
pin cannot float, it must be tied to GND or Vcc directly or through a resistor. During board
testing, this pin retains the functionality of the JTAG scan of the MC68040 for compatibility
purposes. Refer to Section 6 IEEE 1149.1A Test Access Port (JTAG) for details concern-
ing IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture .
A.4 DATA LATCH AND MULTIPLEXED BUS MODES
The MC68LC040 does not implement the data latch or multiplexed modes of operation. The
CDIS pin is ignored at the rising edge of reset. All timing and drive capabilities of the
MC68LC040 are equivalent to those of the MC68040 in small output buffer impedance
mode.
A.5 FLOATING-POINT UNIT (FPU)
The FPU is not implemented on the MC68LC040. All floating-point instructions cause an
unimplemented floating-point exception to be taken with a new eight-word stack frame (for-
mat $4). The stack frame contains the status register (SR), program counter (PC), vector off-
set, effective address of the operand (where applicable), and PC value of the
unimplemented floating-point instruction.
A.5.1 Unimplemented Floating-Point Instructions and Exceptions
All legal MC68040 and MC68881/MC68882 floating-point instructions are defined as unim-
plemented floating-point instructions on the MC68LC040. These instructions generate a for-
mat $4 stack frame during exception processing before taking an F-line exception. These
instructions trap as an F-line exception, and the F-line exception handler can emulate them
in software to maintain user-object-code compatibility.
The MC68LC040 assists the emulation process by distinguishing unimplemented float-
ing-point instructions from other unimplemented F-line instructions. To aid emulation, the
effective address is calculated and saved in the format $4 stack frame. This simplifies and
speeds up the emulation process by eliminating the need for the emulation routine to deter-
mine the effective address and by providing information required to emulate the instruction
on the exception stack frame in the supervisor address space. However, the floating-point
instruction can reside in user space; therefore, the floating-point unimplemented exception
handler may need to access user instruction space. The following processing steps occur
for an unimplemented floating-point instruction:
MOTOROLA
1. When an unimplemented floating-point instruction is encountered, the instruction is
2. The processor waits for all previous integer instructions, write-backs, and associated
partially decoded, and the effective address is calculated, if required.
exception processing to complete before beginning exception processing for the un-
implemented floating-point instruction. Any access error that occurs in completing the
write-backs causes an access error exception, and the resulting stack frame indicates
Freescale Semiconductor, Inc.
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M68040 USER’S MANUAL
MC68LC040
REV2.3 (01/29/2000)
A-5