MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 557

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

12
12-32
12.6.1 Cache Implementation
AS until the decision is valid. Otherwise, spurious assertions of the AS signal
The cache control circuit (B) contains all logic required to clear or create
whether a hit or miss has occurred and the timing logic that is required to
the assertion of STERM by the cache controller (see Equation 12-3 of Table
the STERM signal. Qualifying STERM with AS is not necessary assuming the
tation of valid address by the MC68030 to the assertion of STERM by the
the processor.
An example organization of an external cache is shown in Figure 12-15. With
this organization, the cache timing controller does not terminate a bus cycle
"miss". When a hit decision is made, the cache controller asserts the STERM
signal and also blocks propagation of AS (A) to the external system. If the
cache decision cannot be completed before AS would normally be asserted
are likely to occur.
cache entries. Also contained in (B) is the decision logic required to determine
design of this cache is from the output of valid address by the MC68030 to
appropriate setup and hold times are respected when AS is asserted. Op-
erating at 20 MHz with no wait states, 21 ns are available from the presen-
cache controller while 46 ns are available from valid address to data valid at
size, cost, or other consideration, the system designer may choose to utilize
an early termination approach, as discussed above, that increases the de-
cision time available to the cache controller by meeting the critical path from
address valid to BERR/HALT asserted (see Equation 12-5 of Table 12-2). The
termination or late retry function.
tasks. Conversely, if the cache size is relatively large and the period between
context switches is relatively small, the cache may provide an efficient sharing
of entries.
until the cache has had sufficient time to validate the access as a " h i t " or a
by the MC68030, some provision must be made to delay the propagation of
prevent propagation of the "hit" signal until the lookup and compare circuitry
has had sufficient time to generate a valid decision. The critical path in the
12-2). After a cache hit decision has been made, the hit signal directly drives
If the access times cannot be met due to the particular cache architecture,
only required changes to the cache structure shown in Figure 12-17 is the
generation of STERM. Figure 12-18 shows an example circuit that could be
positioned between the MC68030 and the external cache to provide the early
MC68030 USER'S MANUAL
MOTOROLA