MC68030RC33C Freescale Semiconductor, MC68030RC33C Datasheet - Page 183

• Manufacturer Part Number: MC68030RC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

IN
7-22
7.2.4 Address, Size, and Data Bus Relationships
D31
I
Figure 7-17. Misaligned Cachable Long-Word Transfer from Long-Word Bus
The data transfer examples show how the MC68030 drives data onto or
the combinations of the size signals and address signals that are used to
them. The port size also affects the generation of these enable signals as
W for 16-bit ports, and L for 32-bit ports. The letters B, W, and L imply that
the byte enable signal should be true for that port size. A dash (--) implies
that the byte enable signal does not apply.
generate byte enable signals for each of the four sections of the data bus for
shown in the table. The four columns on the right correspond to the four
The MC68030 always drives all sections of the data bus because, at the start
of a write cycle, the bus controller does not know the port size. The byte
enable signals in the table apply only to read operations that are not to be
which the data is cached, the addressed port must drive all sections of the
receives data from the correct byte sections of the data bus. Table 7-7 shows
noncachable read cycles and all write cycles if the addressed device requires
byte enable signals. Letters B, W, and L refer to port sizes: B for 8-bit ports,
internally cached and to write operations. For cachable read cycles, during
bus on which it resides.
OPO
MSB
LONG WORD OPERAND (REGISTER)
OP1
LONG WORD MEMORY
UMB
DATA BUS
t
LMB
OP2
MC68030 USER'S MANUAL
I
I
31
31
LSB
OP3
PR2
D0
0
I
I
I
SIZ1
0
1
PR,
SIZO
CACHE ENTRIES
0
1
MC68030
I
A2
0
1
PR
A1
I
0
AO
I
0
I
DSACKI
MOTOROLA
MEMORY CONTROL
L
L
0
0
I
DSACKO
L
L